Register Descriptions

Table 10-3. Interrupt Controller Memory Map (continued)

Module Offset

Bits[31:24]

Bits[23:16]

 

Bits[15:8]

Bits[7:0]

 

 

 

 

 

 

0x60

ICR32

ICR33

 

ICR34

ICR35

 

 

 

 

 

 

0x64

ICR36

ICR37

 

ICR38

ICR39

 

 

 

 

 

 

0x68

ICR40

ICR41

 

ICR42

ICR43

 

 

 

 

 

 

0x6C

ICR44

ICR45

 

ICR46

ICR47

 

 

 

 

 

 

0x70

ICR48

ICR49

 

ICR50

ICR51

 

 

 

 

 

 

0x74

ICR52

ICR53

 

ICR54

ICR55

 

 

 

 

 

 

0x78

ICR56

ICR57

 

ICR58

ICR59

 

 

 

 

 

 

0x7C

ICR60

ICR61

 

ICR62

ICR63

 

 

 

 

 

 

0x80-0xDC

 

 

Reserved

 

 

 

 

 

 

 

0xE0

SWIACK

 

 

Reserved

 

 

 

 

 

 

 

0xE4

L1IACK

 

 

Reserved

 

 

 

 

 

 

 

0xE8

L2IACK

 

 

Reserved

 

 

 

 

 

 

 

0xEC

L3IACK

 

 

Reserved

 

 

 

 

 

 

 

0xF0

L4IACK

 

 

Reserved

 

 

 

 

 

 

 

0xF4

L5IACK

 

 

Reserved

 

 

 

 

 

 

 

0xF8

L6IACK

 

 

Reserved

 

 

 

 

 

 

 

0xFC

L7IACK

 

 

Reserved

 

 

 

 

 

 

 

10.3 Register Descriptions

10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)

The IPRHn and IPRLn registers, Figure 10-1and Figure 10-2,are each 32 bits in size, and provide a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of the interrupt mask register does not affect the IPRn. The IPRn is cleared by reset. The IPRn is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero.

10-6

MCF5282 User’s Manual

MOTOROLA

Page 234
Image 234
Motorola MCF5282, MCF5281 user manual Interrupt Pending Registers IPRHn, IPRLn