Motorola MCF5281 Breakpoint/Test Mode Select BKPT/TMS, Development Serial Input/Test Data DSI/TDI

MCF5282 External Signals

asserted-to-negated transition only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to VDD. Tying TRST to ground places the JTAG controller in test logic reset state immediately. Tying it to VDD causes the JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.

14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS)

Debug mode operation: If JTAG_EN is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug mode.

JTAG mode operation: TMS is selected. The TMS input provides information to determine the JTAG test operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state. This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up resistor so that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to VDD.

14.2.14.4 Development Serial Input/Test Data (DSI/TDI)

Debug mode operation: If JTAG_EN is low, DSI is selected. DSI provides the single-bit communication for debug module commands.

JTAG mode operation: TDI is selected. TDI provides the serial data port for loading the various JTAG boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge. TDI has an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it should be tied to VDD.

14.2.14.5 Development Serial Output/Test Data (DSO/TDO)

Debug mode operation: DSO is selected. DSO provides single-bit communication for debug module responses.

JTAG mode operation: TDO is selected. The TDO output provides the serial data port for outputting data from JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in the instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test data, it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices having JTAG.

14.2.14.6 Test Clock (TCLK)

TCK is the dedicated JTAG test logic clock independent of the MCF5282 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground.

MOTOROLA Chapter 14. Signal Descriptions 14-31