Digital Control Subsystem

27.8.7.4Periodic Timer Continuous-Scan Mode

The QADC includes a dedicated periodic timer for initiating a scan sequence on queue 1 and/or queue 2. A programmable timer interval ranging from 27 to 217 times the QCLK period in binary multiples can be selected. The QCLK period is prescaled down from the MCU clock.

When a periodic timer continuous-scan mode is selected, the timer begins counting. After the programmed interval elapses, the timer generated trigger event starts the appropriate queue. The QADC automatically performs the conversions in the queue until an end-of-queue condition or a pause is encountered. When a pause occurs, the QADC waits for the periodic interval to expire again, then continues with the queue. Once EOQ has been detected, the next trigger event causes queue execution to restart with the first CCW in the queue.

The periodic timer generates a trigger event whenever the time interval elapses. The trigger event may cause queue execution to continue following a pause or queue completion or may be considered a trigger overrun. As with all continuous-scan queue operating modes, software action is not needed between trigger events. Because both queues may be triggered by the periodic/interval timer, see Section 27.8.9 for a summary of periodic/interval timer reset conditions.

27.8.8 QADC Clock (QCLK) Generation

Figure 27-42is a block diagram of the QCLK subsystem. The QCLK provides the timing for the A/D converter state machine which controls the timing of the conversion. The QCLK is also the input to a 17-stage binary divider which implements the periodic/interval timer. To retain the specified analog conversion accuracy, the QCLK frequency (fQCLK) must be within the tolerance specified in MCF5282 Electrical Characteristics.

Before using the QADC, the prescaler must be initialized with values that put the QCLK within the specified range. Though most applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted.

MOTOROLA

Chapter 27. Queued Analog-to-Digital Converter (QADC)

27-57

Page 641
Image 641
Motorola MCF5281, MCF5282 user manual Qadc Clock Qclk Generation, Periodic Timer Continuous-Scan Mode