INDEX

clock module CLKMOD1–0, 9-5

clock output (CLKOUT), 9-5,14-22EXTAL,9-4,14-22

RSTOUTl, 9-5XTAL, 9-5,14-22

debug

breakpoint (BKPT), 29-2

breakpoint/test mode select (BKPT/TMS), 14-31CLKOUT, 29-2

debug data (DDATA3–0), 14-32,29-2development serial clock (DSCLK), 29-2

development serial clock/test reset (DSCLK/TRST), 14-30

development serial input (DSI), 29-2

development serial input/test data (DSI/TDI), 14-31

development serial output (DSO), 29-2

development serial output/test data (DSO/TDO), 14-31

JTAG_EN, 14-30

processor status (PST3–0), 29-2processor status output (PST3–0), 14-32test clock (TCLK), 14-31

description by pin, 32-3DMA timers

timer 0 input (DTIN0), 14-28timer 0 output (DTOUT0), 14-28timer 1 input (DTIN1), 14-28timer 1 output (DTOUT1), 14-28timer 2 input (DTIN2), 14-28timer 2 output (DTOUT2), 14-28timer 3 input (DTIN3), 14-29timer 3 output (DTOUT3), 14-29

Ethernet

carrier receive sense (ECRS), 14-24collision (ECOL), 14-24management data (EMDIO), 14-23management data clock (EMDC), 14-23receive clock (ERXCLK), 14-24receive data 0 (ERXDO), 14-24receive data 3–1 (ERXD3–1), 14-25receive data valid (ERXDV), 14-24receive error (ERXER), 14-25transmit clock (EXTCLK), 14-23transmit data 0 (ETXD0), 14-23transmit data 1–3 (ETXD3–1), 14-24transmit enable (ETXEN), 14-23transmit error (ETXER), 14-24

external boot mode, 14-17FlexCAN

receive (CANRX), 14-26transmit (CANTX), 14-26

general purpose timers

external clock input (SYNCx), 14-27,20-4GPTB3–0, 14-27

GPTn2–0, 20-3GPTn3, 20-4GPTx3–0, 14-27

I2C

serial clock (SCL), 14-26serial data (SDA), 14-26

interrupts IRQ7–1, 14-23

JTAG JTAG_EN, 31-3TCLK, 31-4

test data input/development serial input (TDI/DSI), 31-4

test data output/development serial output (TDO/DSO), 31-5

test mode select/breakpoint (TMS/BKPT), 31-4

test reset/development serial clock (TRST/DSCLK), 31-4

overview, 14-1power and reference

VDD, 14-33

VDDA, VSSA, 14-33

VDDF, VSSF, 14-33VDDH, 14-33VDDPLL, VSSPLL, 14-33VPP, 14-33

VRH, VRL, 14-33VSS, 14-33VSTBY, 14-33

QADC

analog input (ANn/ANx), 14-29–14-30analog power (VDDA, VSSA), 27-63analog reference (VRH, VRL), 27-63dedicated digital I/O port supply (VDDH), 27-7external trigger input (ETRIG2–1), 27-6multiplexed address output (MA1–0), 27-6multiplexed analog input (ANx), 27-6

port QA analog input (AN56–55, 53–52), 27-4port QA digital input/output (PQA4–3, 1–0), 27-5port QB analog input (AN3–0), 27-5

port QB digital I/O (PQB3–0), 27-6

QSPI

chip select (QSPI_CS3–0), 14-25serial clock (QSPI_CLK), 14-25summary, 22-2

synchronous serial data input (QSPI_DIN), 14-25

synchronous serial data output (QSPI_DOUT), 14-25

reset controller

reset in (RSTI),14-22,28-2reset out (RSTO), 28-2

SDRAM controller

Index-14

MCF5282 User’s Manual

MOTOROLA

Page 814
Image 814
Motorola MCF5282, MCF5281 user manual Index-14