Motorola MCF5281, MCF5282 user manual Mfd, MFD20, Rfd

Memory Map and Registers

Table 9-4. SYNCR Field Descriptions (continued)

Bit(s)

Name

Description

14–12

MFD

Multiplication Factor Divider. Contain the binary value of the divider in the PLL

feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference

frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL

loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one.

Note: In external clock mode, the MFD[2:0] bits have no effect.

The following table illustrates the system frequency multiplier of the reference

((

frequency 1 in normal PLL mode.

MFD[2:0]

000 2

001

010

011

100

101

110

111

(4x)

(6x)

(8x)(3)

(10x)

(12x)

(14x)

(16x)

(18x)

000 (⎟ 1)

4

6

8

10

12

14

16

18

001 (⎟ 2) 3

2

3

4

5

6

7

8

9

RFD[2:0]

010 (⎟ 4)

1

3/2

2

5/2

3

7/2

4

9/2

011 (⎟ 8)

1/2

3/4

1

5/4

3/2

7/4

2

9/4

100 (⎟ 16)

1/4

3/8

1/2

5/8

3/4

7/8

1

9/8

101 (⎟ 32)

1/8

3/16

1/4

5/16

3/8

7/16

1/2

9/16

110 (⎟ 64)

1/16

3/32

1/8

5/32

3/16

7/32

1/4

9/32

111 (⎟ 128)

1/32

3/64

1/16

5/64

3/32

7/64

1/8

9/64

1

f

= f

ref

x 2(MFD + 2)/2 exp RFD; f

ref

x 2(MFD + 2) ≤ 80 MHz, f

≤ 66.67 MHz

2

sys

sys

MFD = 000 not valid for fref < 3 MHz

3

Default value out of reset

11

LOCRE

Loss-of-clock reset enable. Determines how the system handles a loss-of-clock

condition. When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in

SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an

immediate reset. To prevent an immediate reset, the LOCRE bit must be cleared

before entering stop mode with the PLL disabled.

1 Reset on loss-of-clock

0 No reset on loss-of-clock

Note: In external clock mode, the LOCRE bit has no effect.

10–8

RFD

Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL

frequency divisor. See table in MFD bit description. Changing RFD[2:0] does not affect

the PLL or cause a relock delay. Changes in clock frequency are synchronized to the

next falling edge of the current system clock. To avoid surpassing the allowable system

operating frequency, write to RFD[2:0] only when the LOCK bit is set.

7

LOCEN

Enables the loss-of-clock function. LOCEN does not affect the loss of lock function.

1 Loss-of-clock function enabled

0 Loss-of-clock function disabled

Note: In external clock mode, the LOCEN bit has no effect.

6

DISCLK

Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds

CLKOUT low.

1

CLKOUT disabled

0

CLKOUT enabled

MOTOROLA Chapter 9. Clock Module 9-7