Motorola MCF5282, MCF5281 user manual BDM Serial Interface, Clkout Dsclk DSI, Dso

Background Debug Mode (BDM)

29.5.2 BDM Serial Interface

When the CPU is halted and PST reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising edge of the processor clock. See Table 29-1.The development system serves as the serial communication channel master and must generate

DSCLK.

The serial channel operates at a frequency from DC to 1/5 of the CLKOUT frequency. The channel uses full-duplex mode, where data is sent and received simultaneously by both master and slave devices. The transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown in Figure 29-12,all state transitions are enabled on a rising edge of CLKOUT when DSCLK is high; that is, DSI is sampled and DSO is driven.

				C1		C2	C3
CLKOUT
DSCLK
DSI					Current
BDM State
	Current		State
Machine
DSO		Past

C4

Next

Next State

Current

Figure 29-12. BDM Serial Interface Timing

DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor clock as well as the DSI. DSO is delayed from the DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events in the debug module’s serial state machine are based on the processor clock rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each bit exchange. The MSB is transferred first. Because DSO changes state based on an internally-recognized rising edge of DSCLK, DSDO cannot be used to indicate the start of a serial transfer. The development system must count clock cycles in a given transfer. C1–C4 are described as follows:

•C1—First synchronization cycle for DSI (DSCLK is high).

•C2—Second synchronization cycle for DSI (DSCLK is high).

•C3—BDM state machine changes state depending upon DSI and whether the entire input data transfer has been transmitted.

•C4—DSO changes to next value.

29-18 MCF5282 User’s Manual MOTOROLA