Motorola MCF5282, MCF5281 user manual Receiver, Transmitter Timing Diagram

Operation
		C1 in transmission
UTXDn	C11	C2	C3	Break	C4
Transmitter
Enabled

USRn[TxRDY]
internal	W2
module
select	C11	C2

UCTSn3

W C3

			W
Start	C4 Stop		C5
break		break	not

transmitted

C6

C6

	n4	Manually asserted
URTS
		by BIT-SETcommand

1Cn = transmit characters

2W = write

3UMR2n[TxCTS] = 1

4UMR2n[TxRTS] = 1

Figure 23-20. Transmitter Timing Diagram

Manually asserted

23.5.2.2Receiver

The receiver is enabled through its UCRn, as described in Section 23.3.5, “UART Command Registers (UCRn).”

When the receiver detects a high-to-low (mark-to-space) transition of the start bit on URXD, the state of URXD is sampled eight times on the edge of the bit time clock starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If URXD is sampled high, the start bit is invalid and the search for the valid start bit begins again.

If URXD is still low, a valid start bit is assumed and the receiver continues sampling the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the URXD input is sampled on the rising edge of the programmed clock source. The lsb is received first. The data is then transferred to a receiver holding register and USRn[RxRDY] is set. If the character is less than eight bits, the most significant unused bits in the receiver holding register are cleared.

23-22 MCF5282 User’s Manual MOTOROLA