Motorola MCF5281, MCF5282 user manual Jtag and Boundary Scan Timing

JTAG and Boundary Scan Timing

33.15 JTAG and Boundary Scan Timing

Table 33-23. JTAG and Boundary Scan Timing

Num		Characteristics1	Symbol	Min	Max	Unit
1	TCLK Frequency of Operation		fJCYC	DC	1/4	fsys
2	TCLK Cycle Period		tJCYC	4	—	tCYC
3	TCLK Clock Pulse Width		tJCW	25.0	—	ns
4	TCLK Rise and Fall Times		tJCRF	0.0	3.0	ns
5	Boundary Scan Input Data Setup Time to TCLK Rise		tBSDST	5.0	—	ns
6	Boundary Scan Input Data Hold Time after TCLK Rise		tBSDHT	25.0	—	ns
7	TCLK Low to Boundary Scan Output Data Valid		tBSDV	0.0	30.0	ns
8	TCLK Low to Boundary Scan Output High Z		tBSDZ	0.0	30.0	ns
9	TMS, TDI Input Data Setup Time to TCLK Rise		tTAPBST	5.0	—	ns
10	TMS, TDI Input Data Hold Time after TCLK Rise		tTAPBHT	10.0	—	ns
11	TCLK Low to TDO Data Valid		tTDODV	0.0	25.0	ns
12	TCLK Low to TDO High Z		tTDODZ	0.0	8.0	ns
13		Assert Time	tTRSTAT	100.0	—	ns
	TRST
14		Setup Time (Negation) to TCLK High	tTRSTST	10.0	—	ns
	TRST

1JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing

	2
3	3

TCLK	VIH
(input)		VIL
4			4

Figure 33-15. Test Clock Input Timing

MOTOROLA Chapter 33. Electrical Characteristics 33-25