Motorola MCF5281, MCF5282 user manual FlexCAN Error Counters

Functional Overview

25.4.9 FlexCAN Error Counters

There are two error counters in the FlexCAN: transmit error counter (TXECTR), and receive error counter (RXCTR). The rules for increasing and decreasing these counters are described in the CAN protocol, and are fully implemented in the FlexCAN. Each counter comprises the following:

•8 bit up/down counter

•Increment by 8 (Rx_Err_Counter also by 1)

•Decrement by 1

•Avoid decrement when equal to zero

•Rx_Err_Counter preset to a value 119 ≤ x ≤ 127

•Value after reset = zero

•Detect values for Error Passive, Bus Off and Error Active transitions and for alerting the host.

Both counters are read only (except for Test/Freeze/Halt modes).

The FlexCAN responds to any bus state as described in the protocol, e.g. transmit error active or error passive flag, delay its transmission start time (Error Passive) and avoid any influence on the bus when in Bus Off state. The following are the basic rules for FlexCAN bus state transitions:

•If the value of TXCTR or RXCTR increases to be greater than or equal to 128, the FCS field in the error status register is updated to reflect it (set Error Passive state).

•If the FlexCAN state is Error Passive, and either TXCTR counter or RXCTR then decrements to a value less than or equal to 127 while the other already satisfies this condition, the ESTAT[FCS] field is updated to reflect it (set Error Active state).

•If the value of the TXCTR increases to be greater than 255, the ESTAT[FCS] field is updated to reflect it (set Bus Off state) and an interrupt may be issued. The value of TXCTR is then reset to zero.

•If the FlexCAN state is Bus_Off, then TXCTR, together with an internal counter are cascaded to count the 128 occurrences of 11 consecutive recessive bits on the bus. Hence, TXCTR is reset to zero, and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the TXCTR. When TXCTR reaches the value of 128, ESTAT[FCS] is updated to be Error Active, and both error counters are reset to zero. At any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero, but does NOT affect the TXCTR value.

•If during system start-up, only one node is operating, then its TXCTR increases with each message it’s trying to transmit as a result of ACK_ERROR. A transition to bus state Error Passive should be executed as described, while this device never enters the Bus_Off state.

MOTOROLA Chapter 25. FlexCAN 25-15