Motorola MCF5281, MCF5282 user manual CSCRn Field Descriptions

			Chip Select Registers
			Table 12-8. CSCRn Field Descriptions
Bits	Name		Description
15–14	—	Reserved, should be cleared.
13–10	WS	Wait states. The number of wait states inserted before an internal transfer acknowledge is generated
		(WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA must be asserted by
		the external system regardless of the number of wait states generated. In that case, the external
		transfer acknowledge ends the cycle. An external TA supercedes the generation of an internal TA.
9	—	Reserved, should be cleared.
8	AA	Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses
		specified by the chip select address.
		0	No internal TA is asserted. Cycle is terminated externally.
		1	Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding	CS	n and the
			external system asserts an external TA before the wait-state countdown asserts the internal TA, the
			cycle is terminated. Burst cycles increment the address bus between each internal termination.
7–6	PS	Port size. Specifies the width of the data associated with each chip select. It determines where data is
		driven during write cycles and where data is sampled during read cycles. See Section 12.3.1.1.
		00 32-bit port size. Valid data sampled and driven on D[31:0]
		01 8-bit port size. Valid data sampled and driven on D[31:24]
		1x	16-bit port size. Valid data sampled and driven on D[31:16]
5	BEM	Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must
		be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the
		appropriate mode of byte enable in support of these SRAMs.
		0	BS is not asserted for read. BS is asserted for data write only.
		1	BS is asserted for read and write accesses.
4	BSTR	Burst read enable. Specifies whether burst reads are used for memory associated with each						n.
						CS
		0	Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
			example, a longword read from an 8-bit port is broken into four 8-bit reads.
		1	Enables data burst reads larger than the specified port size, including longword reads from 8- and
			16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
3	BSTW	Burst write enable. Specifies whether burst writes are used for memory associated with each							n.
							CS
		0	Break data larger than the specified port size into individual port-sized, non-burst writes. For
			example, a longword write to an 8-bit port takes four byte writes.
		1	Enables burst write of data larger than the specified port size, including longword writes to 8 and
			16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports.
2–0	—	Reserved, should be cleared.

MOTOROLA Chapter 12. Chip Select Module 12-9