Motorola MCF5282, MCF5281 user manual Signal Name Abbreviation Function, Clock and Reset Signals

Overview

Table 14-1. MCF5282 Signal Description (Continued)

Signal Name		Abbreviation			Function		I/O	Page
SDRAM write enable					Asserted to signify that a DRAM write		O	14-21
		DRAMW
					cycle is underway. Negated to indicate
					a read cycle.
SDRAM bank selects					Interface to the chip-select lines of the		O	14-21
		SDRAM_CS[1:0]
					SDRAMs within a memory block.
SDRAM clock enable		SCKE			SDRAM clock enable.		O	14-21
				Clock and Reset Signals
Reset in		RSTI			Asserted to enter reset exception		I	14-22
					processing.
Reset out					Automatically asserted with		O	14-22
		RSTO				RSTI.
					Negation indicates that the PLL has
					regained its lock.
EXTAL	EXTAL				Driven by an external clock except		I	14-22
					when used as a connection to the
					external crystal.
XTAL		XTAL			Internal oscillator connection to the		O	14-22
					external crystal.
Clock output	CLKOUT				Reflects the system clock.		O	14-22
			Chip Configuration Module
Clock mode	CLKMOD[1:0]				Clock mode select		I	14-22
Reset configuration	RCON				Reset configuration select		I	14-22
				External Interrupt Signals
External interrupts					External interrupt sources.		I	14-23
		IRQ[7:1]
				Ethernet Module Signals
Management data		EMDIO			Transfers control information between		I/O	14-23
					the external PHY and the media
					access controller.
Management data clock		EMDC			Provides a timing reference to the		O	14-23
					PHY for data transfers on the EMDIO
					signal.
Transmit clock		ETXCLK			Provides a timing reference for		I	14-23
					ETXEN, ETXD[3:0], and ETXER.
Transmit enable		ETXEN			Indicates when valid nibbles are		O	14-23
					present on the MII.
Transmit data 0		ETXD0			Serial output Ethernet data.		O	14-23
Collision	ECOL				Asserted to indicate a collision.		I	14-24
Receive clock	ERXCLK				Provides a timing reference for		I	14-24
					ERXDV, ERXD[3:0], and ERXER.

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