Programming Model

Field

Reset

R/W

31

16

PADDR1

Uninitialized

R/W

15

0

Field

Reset

R/W Address

PADDR1

Uninitialized

R/W

IPSBAR + 0x10E4

Figure 17-14. Physical Address Low Register (PALR)

Table 17-23. PALR Field Descriptions

Bits

Name

Description

 

 

 

31–0

PADDR1

Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits

 

 

7:0) of the 6-byte individual address to be used for exact

 

 

match, and the Source Address field in PAUSE frames.

 

 

 

17.5.4.12 Physical Address High Register (PAUR)

The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) used for transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized by the user.

Field

Reset

R/W

31

16

PADDR2

Uninitialized

R/W

15

0

Field

Reset

R/W Address

TYPE

1000_1000_0000_1000

R

IPSBAR + 0x10E8

Figure 17-15. Physical Address High Register (PAUR)

17-36

MCF5282 User’s Manual

MOTOROLA

Page 392
Image 392
Motorola MCF5282, MCF5281 user manual Physical Address High Register Paur, PADDR1, PADDR2, Type