Functional Description

When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without having to wait for the count to reach 0x0000.

PIT CLOCK

 

 

 

 

 

 

COUNTER

0x0002

0x0001

0x0000

0x0005

 

 

MODULUS

 

 

 

 

 

 

 

 

0x0005

 

 

 

PIF

Figure 19-5. Counter Reloading from the Modulus Latch

19.6.2 Free-Running Timer Operation

This mode of operation is selected when the RLD bit in PCSR is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.

When the counter reaches a count of 0x0000, the PIF flag is set in PCSR. If the PIE bit is set in PCSR, the PIF flag issues an interrupt request to the CPU.

When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without having to wait for the count to reach 0x0000.

PIT CLOCK

 

 

 

 

 

 

COUNTER

0x0002

0x0001

0x0000

0xFFFF

 

 

MODULUS

 

 

 

 

 

 

 

 

0x0005

 

 

 

PIF

Figure 19-6. Counter in Free-Running Mode

19.6.3 Timeout Specifications

The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the system clock as selected by the PRE[3:0] bits in PCSR. The PM[15:0] bits in PMR select the timeout period.

PRE[3:0] ⋅ (PM[15:0] + 1) ⋅ 2 Timeout period = --------------------------------------------------------------------------

system clock

MOTOROLA

Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3)

19-7

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Motorola MCF5281, MCF5282 Free-Running Timer Operation, Timeout Specifications, System clock, PIT Clock Counter, Modulus