Interface Features

Acknowledge bit generation/detection

Bus-busy detection

Figure 24-1is a block diagram of the I2C module.

Internal Bus

IRQ

Address

Data

Registers and ColdFire Interface

Address Decode

Data MUX

I2C Frequency

Divider Register

(IFDR)

 

I2C Control

 

 

I2C Status

 

 

 

Register

 

 

Register

 

 

 

(I2CR)

 

 

 

(I2SR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C Data

I2C Address

I/O Register

Register

(I2DR)

(IADR)

Clock Control

Start, Stop,

and

Arbitration

Control

In/Out

Data

Shift

Register

Input Sync

Address Compare

SCL SDA

Figure 24-1. I2C Module Block Diagram

Figure 24-1shows the relationships of the I2C registers, listed below:

I2C address register (I2ADR)

I2C frequency divider register (I2FDR)

I2C control register (I2CR)

I2C status register (I2SR)

I2C data I/O register (I2DR)These registers are described in Section 24.5, “Programming Model.”

24-2

MCF5282 User’s Manual

MOTOROLA

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Motorola MCF5282, MCF5281 user manual Acknowledge bit generation/detection Bus-busy detection, Ifdr, Iadr, Scl Sda