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Motorola MCF5281, MCF5282 user manual Conversion Command Word Table

Models: MCF5282 MCF5281

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Digital Control Subsystem

NOTE

Interval timer single-scan mode does not start the periodic/interval timer until the single-scan enable bit is set.

These conditions will cause a pulsed reset of the periodic/interval timer during use:

•A queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue 2 is already using the timer

•A queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue 1 is not in a mode which uses the periodic/interval timer

•Roll over of the timer

During stop mode, the periodic/interval timer is held in reset. Because stop mode causes QACR1 and QACR2 to be reset to 0, a valid periodic or interval timer mode must be written after leaving stop mode to release the timer from reset.

When QADC debug mode is entered and a periodic or interval timer mode is selected, the timer counter is reset after the conversion in progress completes. When the periodic or interval timer mode has been enabled (the timer is counting), but a trigger event has not been issued, debug mode takes effect immediately, and the timer is held in reset. Removal of the QADC debug condition restarts the counter from the beginning. Refer to Section 27.3.1 for more information.

27.8.10 Conversion Command Word Table

The conversion command word (CCW) table is 64 half-word (128 byte) long RAM with 10 bits of each entry implemented. The CCW table is written by the user and is not modified by the QADC. Each CCW requests the conversion of one analog channel to a digital result. The CCW specifies the analog channel number, the input sample time, and whether the queue is to pause after the current CCW. The 10 implemented bits of the CCW can be read and written. The remaining six bits are unimplemented and read as 0s; write operations have no effect. Each location in the CCW table corresponds to a location in the result word table. When a conversion is completed for a CCW entry, the 10-bit result is written in the corresponding result word entry.

The beginning of queue 1 is the first location in the CCW table. The first location of queue 2 is specified by the beginning of queue 2 pointer field (BQ2) in QACR2. To dedicate the entire CCW table to queue 1, place queue 2 in disabled mode and write BQ2 to 64 or greater. To dedicate the entire CCW table to queue 2, place queue 1 in disabled mode and set BQ2 to the first location in the CCW table (CCW0).

Figure 27-43illustrates the operation of the queue structure.

MOTOROLA

Chapter 27. Queued Analog-to-Digital Converter (QADC)

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Motorola MCF5281, MCF5282 user manual Conversion Command Word Table, 43illustrates the operation of the queue structure

Contents

MCF5282 ColdFire Microcontroller User’s Manual HOW to Reach US USA/EUROPE/LOCATIONS not Listed IND IND Contents Timing Assumptions Move Instruction Execution Times Chapter Enhanced Multiply-Accumulate Unit Emac Chapter Static RAM Sram Chapter CacheColdFire Flash Module CFM Chapter System Control Module SCM Chapter Power Management Interrupt Controller Modules Clock Module Chapter External Interface Module EIM Signal DescriptionsChapter Edge Port Module Eport Chapter Chip Select Module Chapter DMA Controller Module Chapter Synchronous Dram Controller Module Chapter Fast Ethernet Controller FEC Chapter Programmable Interrupt Timer Modules PIT0-PIT3 Chapter Watchdog Timer ModuleChapter General Purpose Timer Modules Gpta and Gptb 20.3 Chapter Queued Serial Peripheral Interface Qspi Module Chapter DMA Timers DTIM0-DTIM3 Chapter I2C Interface Chapter Uart Modules Chapter FlexCAN Chapter Queued Analog-to-Digital Converter Qadc Chapter General Purpose I/O Module 27.4.7 Chapter Debug Support Reset Controller Module Chapter Ieee 1149.1 Test Access Port Jtag Chapter Chip Configuration Module CCM Paragraph Title Number 31.6.2 Nonscan Chain Operation 31-12 Electrical CharacteristicsChapter Mechanical Data Appendix a Register Memory Map Title Number Illustrations 10-7 13-4 17-13 20-20 23-10 25-31 Qadc Status Register 0 QASR0 27-22 27-12 27-53 29-39WDMREG BDM Command Format 29-36 29-40 Tables Charge Pump Current and MFD in Normal Mode Operation 10-13 15-18 17-30 20-23 25-21 27-13 29-43 33-21 Timer Module AC Timing Specifications 33-24 33-22 Organization Audience Organization Xlv General Information Suggested ReadingColdFire Documentation Conventions Table i. Acronyms and Abbreviated Terms Acronyms and AbbreviationsMeaning Opcode Wildcard Terminology ConventionsTable ii. Notational Conventions Operand Syntax PST ACCCCR Port Name MSW LSW SST Revision HistoryTable iii provides a revision history for this document Table iii. Revision History Number Release Revision Date Substantive ChangesFrsr Liv RAMBAR.’ 10.3.6/10-11 Substantive Changes Section/Page Revision Number Chapter Overview MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Block Diagram Cache Cache ConfigurationConfiguration Tag Address Data Array Address Version 2 ColdFire Core Flash SramDebug Module External Interface Module EIM System Control Module Interrupt Controllers INTC0/INTC1 Power ManagementChip Select General Input/Output Ports Uart Modules Test Access Port General-Purpose Timers GPTA/GPTB DMA Timers DTIM0-DTIM3Periodic Interrupt Timers PIT0-PIT3 DMA Controller Software Watchdog TimerPhase Locked Loop PLL Reset MCF5282-Specific Features MCF5282-Specific Features Dsoc Processor PipelinesIAG Fifo User Programming Model Processor Register Description Program Counter PC Data Registers D0-D7Address Registers A0-A6 Stack Pointer A7 Bits Name Description Condition Code Register CCR Supervisor Programming Model Emac Programming Model System Byte Condition Code Register CCR Status Register SRBits Supervisor/User Stack Pointers A7 and OTHERA7 Cache Control Register Cacr Access Control Registers ACR0, ACR1Programming Model Vector Base Register VBR Name CPU Space Rc Written with Register Name Additions to the Instruction Set ArchitectureLocal Memory Registers ISA Revision A+ New Instructions Exception Processing OverviewInstruction Description Vector Stacked Program Assignment NumberS Offset Hex Counter Exception Vector Assignments Format Field Encodings Exception Stack Frame Definition0x100-0x3FC Next FS30 Definition Access Error ExceptionFault Status Encodings Processor Exceptions Privilege Violation Address Error ExceptionIllegal Instruction Exception Divide-By-Zero Unimplemented Line-F Opcode Unimplemented Line-A OpcodeDebug Interrupt Trap Instruction Exception RTE and Format Error ExceptionFault-on-Fault Halt Reset Exception MAC DIV Emac FPU MMU ISA Debug VER REV VER D0 Hardware Configuration Info Field DescriptionMAC Busw DCA Dcsiz RAM1SIZ ROM1SIZ ICA Icsiz RAM0SIZ ROM0SIZICA 32KB RAM 4KB RAM8KB RAM 16KB RAM Timing Assumptions Instruction Execution Timing 10. Misaligned Operand References Move Instruction Execution TimesAddress10 Size Kbus Additional Operations CR/W 12. Move Long Execution Times 11. Move Byte and Word Execution TimesSource Destination Ax+ D16,Ax D8,Ax,Xi Xxx.wl 14. Two Operand Instruction Execution Times Standard One Operand Instruction Execution TimesStandard Two Operand Instruction Execution Times 13. One Operand Instruction Execution Times Standard Two Operand Instruction Execution Times D16,PC D8,PC,Xn*SF Miscellaneous Instruction Execution Times15. Miscellaneous Instruction Execution Times Effective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl 16. Emac Instruction Execution Times Emac Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,X Xxx.wl #xxx 18. BRA, Bcc Instruction Execution Times Branch Instruction Execution TimesColdFire Instruction Set Architecture Enhancements 17. General Branch Instruction Execution Times Instruction Format OperationAssembler Syntax Attributes Assembler Syntax BYTEREV.L Dx Attributes Byte Reverse Register ByterevCondition Codes Old Dx310 New Dx310 Find First One in Register Supported Starting with ISA A+ Store/Load Status Register StrldsrAssembler SyntaxSTRLDSR #data Multiply-Accumulate Unit Chapter Enhanced Multiply-Accumulate Unit Emac Introduction to the MAC Multiply-Accumulate Functionality Diagram Infinite Impulse Response IIR Filter General Operation Fractional Alignment Motorola MAC Status Register Macsr Memory Map/Register Set1describes Macsr fields Macsr Field Descriptions Operational Modes Fractional Operation ModeRounding Summary of S/U, F/I, and R/T Control Bits Saving and Restoring the Emac Programming Model Mask Register Mask Following code performs the Emac state restoreMULS/MULU MAC.sz Ry,RxSF,eay&,Rw 3summarizes Emac unit instructions Command Mnemonic DescriptionEmac Instruction Set Summary Emac Instruction Execution Times Mac Mov Data RepresentationAccumulator Mac Old Mov New Two’s Complement, Signed Fractional Equation MAC Opcodes MACSR.V = Emac Instruction Set Summary MACSR.Z = Emac Instruction Set Summary Motorola Emac Instruction Set Summary MCF5282 User’s Manual Cache Physical Organization Cache FeaturesThis chapter describes the MCF5282 cache operation Cache Physical Organization Interaction with Other Modules Cache Operation Cache Coherency and Invalidation Memory Reference Attributes Initial Fetch Offset vs. Clnf Bits Cache Miss Fetch Algorithm/Line FillsCLNF10 Longword Address Bits CACR31 CACR10 Type of Instruction Fetch Description Instruction Cache Operation as Defined by CACR31 Cache Control Register Cacr Cache Programming ModelCache Registers Memory Map Cache Registers Cenb Cenb CPDCinv Didi Disd Invi Invd Ceib DCM Dbwe DWP Eusp Clnf Ceib Cache Invalidate All as Defined by CACR23, 22, 21 Cache Configuration as Defined by CACR31, 23CACR31 CACR23 CACR22 Configuration Description CACR23 CACR22 CACR21 CACR20 Configuration Operation External Fetch Size Based on Miss Address and Clnf Access Control Registers ACR0, ACR1Bufw Between the processors local bus and the external bus BWE Sram Operation Sram FeaturesSram Programming Model PRI12 Upper Bank Lower Bank Priority Sram Base Address Register RambarPRI1 PRI2 SPV PRI1, PRI2 Sram Base Address Register Sram Initialization Following loop initializes the entire Sram to zero Power ManagementTypical Rambar Setting Examples Sram Initialization Code Sram Programming Model Sram Programming Model MCF5282 User’s Manual Chapter ColdFire Flash Module CFM Features Block Diagram CFM Block Diagram CFM Array Memory Map Memory Map Address Offset from array base Size Description CFM Configuration FieldCFM Configuration Field Flash Base Address Register Flashbar Memory Map BA30 BA29 Flash registers are described in this subsection CFM Configuration Register CfmcrCFM Registers Register Descriptions Divld PRDIV8 CFM Clock Divider Register CfmclkdCfmcr Field Descriptions Bits Name Description Cfmclkd Field Descriptions CFM Security Register Cfmsec SEC150 Description Cfmsec Field Descriptions Cfmprot Field Descriptions CFM Protection Register CfmprotProt Sector CFM Supervisor Access Register CfmsaccPROTECT31 PROTECT2 Cfmsacc Field Descriptions CFM Data Access Register CfmdaccData Cbeif Ccif Pviol Accerr Blank CFM User Status Register CfmustatOnly one Cfmustat bit should be cleared at a time 10. Cfmustat Field Descriptions 12. Cfmcmd User Mode Commands CFM Command Register CfmcmdCommand Name Description Program and Erase Operations CFM OperationRead Operations Write Operations Thus the Flash state machine clock will be Setting the Cfmclkd RegisterConsider the following example for fSYS = 66 MHz Program, Erase, and Verify Sequences Meaning Description Flash Valid Commands13summarizes the valid Flash user commands 13. Flash User Commands 13. Example Program Algorithm Flash User Mode Illegal Operations Stop Mode Flash Security Operation Master Mode Back Door Access ResetErase Verify Check Cbeif Cbeie Interrupt Source Interrupt Flag Local EnableInterrupts 14. CFM Interrupt Sources Interrupts MCF5282 User’s Manual Programming Model Memory Map and Registers Following subsection describes the PMM registers Low-Power Interrupt Control Register LpicrChip Configuration Module Memory Map Memory Map Enbstop Lpicr Field Description Lpmd Stpmd Lvdse Low-Power Control Register LpcrXlpmipl Settings Xlpmipl Interrupts Level Needed to Exit Low-Power Mode Functional Description Low-Power ModesLow-Power Modes PLL/CLKOUT Stop Mode Operation Stop Mode Run ModeWait Mode Doze Mode ColdFire Core Peripheral Behavior in Low-Power ModesStatic Random-Access Memory Sram Peripheral Shut Down Uart Modules UART0, UART1, and UART2 Sdram Controller SdramcChip Select Module DMA Controller DMAC0-DMA3 2.9 I2C Module DMA Timers DMAT0-DMAT3Queued Serial Peripheral Interface Qspi 2.14 I/O Ports Reset ControllerInterrupt Controllers INTC0, INTC1 Fast Ethernet Controller FEC Clock Module Chip Configuration Module Queued Analog-to-Digital Converter Qadc Watchdog TimerProgrammable Interrupt Timers PIT0, PIT1, PIT2 and PIT3 Edge Port FlexCAN General Purpose Timers Gpta and Gptb Functional Description ColdFire Flash Module Jtag Summary of Peripheral State During Low-Power ModesCPU and Peripherals in Low-Power Modes 2.25 BDM BDM QadcJtag Functional Description MCF5282 User’s Manual Overview Features SCM Register Map Memory Map and Register Definition3124 2316 158 Internal Peripheral System Base Address Register Ipsbar Register DescriptionsCache Ipsbar Field Description Memory Base Address Register Rambar BDE Memory Base Address Register Rambar Rambar Field Description Core Watchdog Control Register Cwcr Core Reset Status Register CrsrCrsr Field Descriptions Register Descriptions CWT CWT Time-Out Period Core Watchdog Timer Delay Internal Bus Arbitration Core Watchdog Service Register Cwsr Marb SRAM1 Mpark Rambar CPU DMA EIMFEC Sdramc Overview Round-Robin ModeArbitration Algorithms M2PEN BCR24BIT M3PRTY M2PRTY M0PRTY M1PRTY Fixed ModeFixed Timeout Prklast Lckouttime Bus Master Park Register Mpark Mpark Field Description Features System Access Control Unit Sacu PACR1 PACR2 PACR3 Memory Map/Register DefinitionSacu Register Memory Map 3128 2724 2320 1916 1512 118 Master Privilege Register MPR Peripheral Access Control Registers Pacr 0-PACR8PACR6 Bits Supervisor Mode User Mode 12. Peripheral Access Control Registers PACRsIpsbar Offset Name Modules Controlled DTIM2 DTIM3 UART2Qspi DTIM0 DTIM1 14. Gpacr Accessctrl Bit Encodings 13. Grouped PeripheralAccess Control RegisterGpacr Field Descriptions EPORT, WDOG, PIT0-PIT3, QADC, GPTA, Gptb 15. Gpacr Address SpaceRegister Space Protected Modules Protected Ipsbar Offset GPACR0 Modes of Operation Normal PLL Mode Clock Module Operation in Low-power Modes Low-power Mode Operation2 11 PLL Mode External Clock Mode Clock Module Block Diagram Block Diagram Name Function Signal DescriptionsSignal Properties Extal Memory Map and Registers Locen Disclk Fwkup STPMD1 STPMD0 Register DescriptionsSynthesizer Control Register Syncr Lolre MFD2 MFD1 MFD0 Locre MFD20 MFDRFD Pllmode Synthesizer Status Register SynsrStpmd OSC Locks Synsr Field Descriptions System Clock Modes Clock ModeFunctional Description System Clock Modes Clock Out and Clock In Relationships Clock Operation During ResetSystem Clock Mode PLL Options System Clock Generation PLL Operation Phase and Frequency Detector PFD Multiplication Factor Divider MFD Charge Pump Current and MFD in Normal Mode OperationCharge Pump/Loop Filter Voltage Control Output VCO PLL Lock Detection PLL Loss of Lock Conditions PLL Loss of Lock Reset Loss of Clock Summary Loss of Clock ResetLoss of Clock Detection Alternate Clock Selection 10. Stop Mode Operation Sheet 1 Loss of Clock in Stop Mode Expected PLL Action 10. Stop Mode Operation Sheet 2Stop NRM ‘LC ‘LK 10. Stop Mode Operation Sheet 3‘LC NRM ‘LK PLL 10. Stop Mode Operation Sheet 4 Modes 10. Stop Mode Operation Sheet 5Lose reference Clock Functional Description MCF5282 User’s Manual 10.1 68K/ColdFire Interrupt Architecture Overview Chapter Interrupt Controller Modules 68K/ColdFire Interrupt Architecture Overview Interrupt Priority Within a Level Interrupt Controller Theory of OperationInterrupt Recognition Interrupt Prioritization Interrupt Vector Determination Interrupt Controller Number Base Address Memory MapInterrupt Controller Base Addresses Interrupt Controller Memory Map Interrupt Pending Registers IPRHn, IPRLn INT Intmask Interrupt Mask Register IMRHn, IMRLnMaskall IMRLn Field Descriptions Interrupt Force Registers INTFRCHn, INTFRCLnIntfrc IRQ Interrupt Request Level Register IRLRn Level PRI Interrupt Acknowledge Level and Priority Register IACKLPRnInterrupt Control Register ICRnx, x = 1, 2 11. IACKLPRn Field Descriptions 12. ICRnx Field Descriptions Interrupt Sources13. Interrupt Source Assignment for INTC0 DTIM2 CAP/REF IIFDTIM0 CAP/REF DTIM1 CAP/REF PIT2 PIF Gptb TOFPIT0 PIF PIT1 PIF 14. Interrupt Source Assignment for INTC1 Software and Level n Iack Registers SWIACKR, L1IACK-L7IACK Vector Prioritization Between Interrupt Controllers Low-Power Wakeup Operation 10-18 Introduction Low-Power Mode OperationIpbus Low-power Mode Eport Operation Mode Exit Edge Port Module Operation in Low-power ModesInterrupt/General-Purpose I/O Pin Descriptions Registers Bits AccessEdge Port Module Memory Map EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 Eport Pin Assignment Register EpparEport Data Direction Register Epddr EPPA7 Edge Port Data Register Epdr Edge Port Interrupt Enable Register EpierEpdd Field Descriptions Edge Port Flag Register Epfr Edge Port Pin Data Register EppdrEpdr Field Descriptions EPF7-EPF1 Epfr Field Descriptions 11-8 Signal Description Chip Select Module Signals1lists signals used by the chip select module Chip Select Module Signals Transfer Size Port Size Byte Enables/Byte Write Enable Signal SettingsD3124 D2316 D158 D70 General Chip Select Operation Chip Select Operation BS2 BS1 BS0 External Boot Chip Select OperationAccesses by Matches in CSARs and DACRs 12.3.1.1 8-, 16-, and 32-Bit Port Sizing Chip Select Registers D1918 External Boot Chip Select ConfigurationD1918 Boot Device/Data Port Size Chip Select Registers 6describes Csarba Chip Select Module RegistersChip Select Address Registers CSAR0-CSAR6 CSARs, -2,specify the chip select base addresses Csmr n Field Descriptions Chip Select Mask Registers CSMR0-CSMR67describes Csmr fields CSARn Field Description PS1 PS0 BEM Bstr Bstw Chip Select Control Registers CSCR0-CSCR68describes CSCRn fields SD,UC No internal TA is asserted. Cycle is terminated externally CSCRn Field Descriptions 12-10 ColdFire Bus Signal Summary Bus and Control SignalsSignal Name Description Clkout Edge Data Transfer Operation Bus CharacteristicsTIP Bus Cycle Execution Chip-Select Module Output Timing Diagram Accesses by Matches in CSCRs and DACRs Bus Cycle States Data Transfer Cycle StatesState Cycle Read Cycle System MCF5282 Write Cycle Write cycle timing diagram is shown in Figure3describes the six states of a basic write cycle Read Cycle with Fast Termination Fast Termination Cycles Burst Cycles Back-to-Back Bus Cycles Line Read Bus Cycles Allowable Line Access PatternsA32 Longword Accesses Line Transfers 13shows timing when internal termination is used 16. Line Write Burst 2-1-1-1, Internal/External Termination Line Write Bus Cycles 17shows a line burst write with one wait-state insertion Misaligned Operands 19. Example of a Misaligned Longword Transfer 32-Bit Port 13-16 Chapter Signal Descriptions MCF5282 Block Diagram with Signal Interfaces Signal Name Abbreviation Function External Memory Interface MCF5282 Signal DescriptionSdram Controller Signals External Interrupt Signals Signal Name Abbreviation FunctionClock and Reset Signals Chip Configuration Module Uart Signals Queued Serial Peripheral Interface Qspi SignalsFlexCAN Signals 2C Signals Debug Support Signals General Purpose Timer SignalsDMA Timer Signals Analog-to-Digital Converter Qadc Signals Test Signals 2lists signals in alphabetical order by abbreviated namePower and Reference Signals Abbreviation Function MCF5282 Alphabetical Signal Index Vddpll TCK External Memory Interface and Ports MCF5282 Signals and Pin Numbers Sorted by FunctionChip Configuration/Mode Selection Secondary Ethernet Chip SelectsSdram Controller External Interrupts Port FlexCAN UARTs General Purpose Timers Queued Analog-to-Digital Converter Qadc DMA TimersDebug and Jtag Test Port Control Power Supplies Single-Chip ModeTest Signal Reset Clock and Reset Signals External Boot ModeListing of signals that do not default to a Gpio function Pin Reset States at Reset Single-Chip Mode Data Bus D310 14.2 MCF5282 External SignalsExternal Interface Module EIM Signals Address Bus A230 Read/Write R/W Output Enable OETransfer Error Acknowledge TEA Transfer Acknowledge TA Transfer Size Encoding Transfer Start TSTransfer In Progress TIP Chip Selects CS60 Sdram Controller Signals Chip Configuration Signals Clock and Reset Signals Ethernet Module Signals External Interrupt Signals Receive Data Valid Erxdv Transmit Error EtxerCollision Ecol Receive Clock Erxclk Queued Serial Peripheral Interface Qspi Signals 14.2.9 I2C Signals FlexCAN SignalsUart Module Signals General Purpose Timer Signals DMA Timer Signals Analog-to-Digital Converter Signals Debug Support Signals Test Clock Tclk Breakpoint/Test Mode Select BKPT/TMSDevelopment Serial Input/Test Data DSI/TDI Development Serial Output/Test Data DSO/TDO Test Test Test SignalsDebug Data DDATA30 Processor Status Outputs PST30 Power and Reference Signals 14-34 Definitions Overview Scas Sras Scke SDRAMCS10 Dramw Block Diagram and Major ComponentsDACR0 DACR1 Command Definition Sdram CommandsSdram Controller Operation Dram controller registers memory map is shown in Table Dram Controller Signals2describes the behavior of Dram signals in synchronous mode Memory Map for Sdramc Registers DCR Field Descriptions Dram Control Register DCRDCR, shown in -2,controls refresh logic 4describes DCR fields Bit Dram Address and Control Registers DACR0/DACR15describes DACRn fields DACRn Field Descriptions 15-7 DMRn Field Descriptions Bit Associated Access Type Access DefinitionDram Controller Mask Registers DMR0/DMR1 6describes DMRn fields Address Pin Row Address Column Address General Synchronous Operation GuidelinesAddress Multiplexing Generic Address Multiplexing Scheme Pins Pins Row ColumnMCF5282 Row Column 15-12 Interfacing Example Burst Page ModePins MCF5282 Sdram Byte Strobe Connections Burst Read Sdram Access Auto-Refresh Operation Burst Write Sdram Access Auto-Refresh Operation Self-Refresh Operation Self-Refresh Operation Initialization Sequence Mode Register Settings Clkout 25. Sdram Example SpecificationsParameter Specification Sdram Example 26. Sdram Hardware Connections Sdram Interface ConfigurationDCR Initialization Dacr Initialization Casl CBM Imrs Bits Name Setting DescriptionDACRs should be programmed as shown in Figure 28. Dacr Initialization Values 29. DMR0 Initialization Values DMR Initialization MCF5282 Pins Sdram Pins Mode Register Initialization Mode Register Initialization30. Mode Register Initialization 31. Mode Register Mapping to MCF5282 A310 Refresh Sequence Mode Register Initialization SequenceInitialization Code Precharge Sequence 15-25 15-26 Chapter DMA Controller Module Channel 0 Channel 1 Channel 2 Channel DMA Module Features DMA Request Control Dmareqc DMA DMA Transfer Overview Memory Map for DMA Controller Module Registers DMA Controller Module Programming Model DAR Source Address Registers SAR0-SAR3Destination Address Registers DAR0-DAR3 SAR BCR Byte Count Registers BCR0-BCR3 BWC Sinc Ssize Dinc Dsize Start DMA Control Registers DCR0-DCR33describes DCRn fields DCRn Field Descriptions Encoding BCR24BIT = BWC 4describes DSRn fields DMA Status Registers DSR0-DSR3DSR n Field Descriptions Done DMA Controller Module Functional DescriptionTransfer Requests Cycle-Steal and Continuous Modes BSY Dual-Address Transfers Data Transfer Modes Channel Prioritization Channel Initialization and StartupProgramming the DMA Controller Module Auto-Alignment Data Transfer Bandwidth Control Termination 16-16 Chapter Fast Ethernet Controller FEC Primary operational modes are described in this section Full and Half Duplex OperationInterface Options 17.2.2.1 10 Mbps and 100 Mbps MII Interface Address Recognition Options 17.2.2.2 10 Mpbs 7-Wire Interface OperationInternal Loopback PAD FEC Top-Level Functional Diagram 17-5 Ecretheren De-Assertion Effect on FEC Initialization SequenceUser Initialization Prior to Asserting Ecretheren Hardware Controlled Initialization Microcontroller Initialization Microcontroller InitializationUser Initialization After Asserting Ecretheren FEC User Initialization Before Ecretheren Network Interface Options MII ModeWire Mode Configuration Signal Description Emac pin FEC Frame Transmission FEC Frame Reception Ethernet Address Recognition Ethernet Address Recognition-Receive Block Decisions Ethernet Address Recognitionq-Microcode Decisions Hash Algorithm Bit DA Bit Hash Hash Decimal Hex Value Destination Address to 6-Bit Hash 17-15 Full Duplex Flow Control Pause Frame Field Specification Collision Handling Inter-Packet Gap IPG TimeInternal and External Loopback Transmission Errors Ethernet Error-Handling Procedure Heartbeat Reception Errors 10. FEC Register Memory Map Top Level Module Memory MapDetailed Memory Map Control/Status Registers Module Memory Map MIB Block Counters Memory Map Mnemonic Description Offset 11. MIB Counters Memory Map Ethernet Interrupt Event Register EIR RegistersFollowing sections describe each register in detail Babr Babt GRA TXF TXB RXF RXB MII Eberr Hberr Ieeetsqe 17-25 Receive Descriptor Active Register Rdar Interrupt Mask Register EimrBabr Babt GRA TXF TXB RXF RXB MII Rdesactive Transmit Descriptor Active Register Tdar Ethernet Control Register ECR Etheren ResetXdesactive 16. ECR Field Descriptions MII Management Frame Register MmfrData Bit Name Description 17. Mmfr Field Descriptions Dispreamble Miispeed MII Speed Control Register MscrDispreamble 19. Programming Examples for Mscr Mibdisable MibidleMibdisable MIB Control Register Mibc FCE Receive Control Register RCRMaxfl FCE Bcrej Prom Miimode DRT Loop Tfcpause Fden Transmit Control Register TCRGTS 22. TCR Field Descriptions Physical Address Low Register PalrTfcpause Type Physical Address High Register PaurPADDR1 PADDR2 Opcode Opcode/Pause Duration Register OPDDescriptor Individual Upper Address Register Iaur 24. Paur Field Descriptions IADDR2 Descriptor Individual Lower Address IalrIADDR1 Bits Name Descriptions GADDR1 Descriptor Group Upper Address GaurDescriptor Group Lower Address Galr 27. Ialr Field Descriptions GADDR2 Fifo Transmit Fifo Watermark Register TfwrXwmrk 30. Tfwr Field Descriptions Fifo Receive Bound Register FrbrRbound Receive Descriptor Ring Start Erdsr Fifo Receive Start Register FrsrRfstart Rdesstart Transmit Buffer Descriptor Ring Start EtsdrXdesstart 34. Etdsr Field Descriptions Receive Buffer Size Register EmrbrRbufsize Driver/DMA Operation with Buffer Descriptors Buffer DescriptorsDriver/DMA Operation with Transmit BDs Driver/DMA Operation with Receive BDs RO1 RO2 Ethernet Receive Buffer Descriptor RxBD Erdsr 36. Receive Buffer Descriptor Field DefinitionsWord Location Field Name Description RO1 Ethernet Transmit Buffer Descriptor TxBD TO1 TO1 TO2 ABC 17-51 17-52 Low-power Mode Watchdog Operation Mode Exit Watchdog Module Operation in Low-power Modes Watchdog timer module has no off-chip signals SignalsRefer to -2for an overview of the watchdog memory map Watchdog Timer Module Memory Map 16-bit WCR configures watchdog timer operationWatchdog Control Register WCR WCR Field Descriptions Watchdog Modulus Register WMR WC9 WC8 Watchdog Service Register WSRWatchdog Count Register Wcntr WMR Field Descriptions WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 WS9 WS8 Chapter Programmable Interrupt Timer Modules PIT0-PIT3 PIT Module Operation in Low-power Modes PIT module has no off-chip signalsLow-power Mode PIT Operation Mode Exit Ipsbar Offset Access For PITx Bits Address Programmable Interrupt Timer Modules Memory Map PRE PIT Control and Status Register PcsrPRE3 PRE2 PRE1 PRE0 Doze Halted OVW PIE PIF RLD PIF PIT Modulus Register PMR PIT Count Register Pcntr Set-and-Forget Timer OperationThis subsection describes the PIT functional operation PIT Clock Counter Free-Running Timer OperationTimeout Specifications System clock PIT Interrupt Requests Interrupt Request Flag Enable Bit TimeoutInterrupt Operation 4shows the interrupt request generated by the PIT Chapter General Purpose Timer Modules Gpta and Gptb GPT Block Diagram Pin Signal DescriptionFunction Reset State Pull-up Name Register Bit GPTn20 GPT Modules Memory Map Ipsbar Offset Bits AccessGPTn3 SYNCn IOS GPT Input Capture/Output Compare Select Register Gptios FOC GPT Compare Force Register GpcforcGPT Output Compare 3 Mask Register GPTOC3M Gptios Field Descriptions OC3D GPT Output Compare 3 Data Register GPTOC3DGPT Counter Register Gptcnt GPTOC3M Field Descriptions Gpten GPT System Control Register 1 GPTSCR1Gptcnt Field Descriptions Gpten Tffca OM3 OL3 OM2 GPT Toggle-On-Overflow Register GpttovGPT Control Register 1 GPTCTL1 TOV EDG3B EDG3A EDG2B EDG2A GPT Interrupt Enable Register GptieGPT Control Register 2 GPTCTL2 11. GPTCL1 Field Descriptions 13. Gptie Field Descriptions GPT System Control Register 2 GPTSCR2 GPT Flag Register 2 GPTFLG2 GPT Flag Register 1 GPTFLG1 PAE Pamod Pedge CLK Paovi PAI GPT Channel Registers GPTCnPulse Accumulator Control Register Gptpactl Ccnt Paclk Pulse Accumulator Flag Register GptpaflgPaovf Paif 19. Gptpaflg Field Descriptions Pulse Accumulator Counter Register GptpacntPacnt Portt GPT Port Data Register GptportGPT Port Data Direction Register Gptddr 22. Gptddr Field Descriptions Input Capture PrescalerOutput Compare Pulse Accumulator Event Counter Mode OM3 OL3 Gated Time Accumulation ModeGeneral-Purpose I/O Ports Pulse Accumulator EDGx OMx OC3Mx Pin Data Driven Comments 23. GPT Settings and Pin FunctionsDir Function Interrupts Reset24lists the interrupt requests generated by the timer Interrupt Request Flag Enable Bit Pulse Accumulator Input Paif Timer Overflow TOFGPT Channel Interrupts CnF Pulse Accumulator Overflow Paovf 20-23 20-24 Chapter DMA Timers DTIM0-DTIM3 Key Features DMA Timer Programming ModelPrescaler Reference Compare Capture ModeOutput Mode DMA Timer Module Memory Map Orri FRR CLK RST DMA Timer Mode Registers DTMRn DTXMR3 DMA Timer Extended Mode Registers DTXMRn2describes the DTMRn fields DTMRn Field Descriptions 3describes the DTXMRn fields DMA Timer Event Registers DTERnDTXMRn Field Descriptions DTERn Field Descriptions DMA Timer Reference Registers DTRRnDMA Timer Capture Registers DTCRn 4describes the DTERn fields DMA Timer Counters DTCNn Using the DMA Timer Modules Code Example T0LOOP Calculating Time-Out Values Module Description Chapter Queued Serial Peripheral Interface Qspi Module Qspi RAM Interface and SignalsQspiclk Internal Bus Interface Qspi Input and Output Signals and FunctionsSignal Name Hi-Z or Actively Driven Function Operation Qspi RAM 0x0F Receive RAMRelative Address Register 0x00 0x01 Baud Rate Selection Command RAMTransmit RAM 66.67 MHz Transfer DelaysQspiclk Frequency as Function of System Clock and Baud Rate System Clock Transfer Length Qspi Registers Programming Model Value Bits per transfer Qspi Mode Register QMR4gives QMR field descriptions QMR Field Descriptions QCD Qspi Delay Register QdlyrQspics Qmrcpol = Qmrcpha = = Qdlyrqcd Qcrcont = = Qdlyrdtl Qdlyr Field Descriptions Qspi Wrap Register QWR5gives Qdlyr field descriptions 6gives QWR field descriptions 7describes QIR fields Qspi Interrupt Register QIRQIR Field Descriptions Qspi Data Register QDR Qspi Address Register QARAddr 8gives QCR field descriptions Command RAM Registers QCR0-QCR15QCR0-QCR15 Field Descriptions QS4 QS5 Programming ExampleQSPICS30 Qspiclk QS2 Qspidout QS3 Qspidin 22-17 22-18 Ucts Urts Urxd Utxd Uart Serial Module Overview Uart Module Memory Map Register DescriptionsIpsbar Offset 3124 2316 158 ERR Uart Mode Registers 1 UMR1n CTS Parity Mode Parity Type PT=2describes UMR1n fields UMR1n Field Descriptions 3describes UMR2n fields Uart Mode Register 2 UMR2nUMR2 n Field Descriptions USRn Field Descriptions Uart Status Registers USRn4describes USRn fields UMR2n Field Descriptions 5describes UCSRn fields Uart Clock Select Registers UCSRnRCS TCS Dtin Uart Command Registers UCRnUCSRn Field Descriptions RCS UCR n Field Descriptions Bits Value Command Description Uart Transmit Buffers UTBn Uart Receive Buffers URBnUCRn Field Descriptions COS CTS Uart Input Port Change Registers UIPCRn7describes UIPCRn fields Uipcr n Field Descriptions 8describes UACRn fields UACRs, shown in -7,control the input enableUart Auxiliary Control Register UACRn Uart Interrupt Status/Mask Registers UISRn/UIMRn 9describes UISRn and UIMRn fields Uart Baud Rate Generator Registers UBG1n/UBG2nUisr n/UIMR n Field Descriptions 11describes UOP1 and UOP0 fields Uart Output Port Command Registers UOP1n/UOP0nUart Input Port Register UIPn 10describes UIPn fields 11. UOP1/UOP0 Field Descriptions IRQ Uart Module Signal DefinitionsUcts Transmitter/Receiver Clock Source 12. Uart Module SignalsProgrammable Divider Sysclk Following sections describe how to calculate baud ratesCalculating Baud Rates System Clock Baud Rates External Clock Transmitter and Receiver Operating ModesTransmitter Therefore UBG1n = 0x00 and UBG2n = 0xD6 23-21 Receiver 20. Transmitter Timing Diagram 21shows receiver functional timing Fifo Stack 23-24 Local Loop-Back Mode Automatic Echo ModeLooping Modes Remote Loop-Back Mode Multidrop Mode 25. Multidrop Mode Timing Diagram Write Cycles Bus OperationProgramming Read Cycles 13. Uart Interrupts Setting up the Uart to Generate Core InterruptsSetting up the Uart to Request DMA Service Interrupt and DMA Request Initialization 14. Uart DMA Requests Register SettingUart Module Initialization Sequence 15shows the Uart module initialization sequence 26. Uart Mode Programming Flowchart Sheet 1 26. Uart Mode Programming Flowchart Sheet 2 26. Uart Mode Programming Flowchart Sheet 3 26. Uart Mode Programming Flowchart Sheet 4 26. Uart Mode Programming Flowchart Sheet 5 23-36 Chapter I2C Interface Interface Features SCL SDA Acknowledge bit generation/detection Bus-busy detectionIfdr Iadr 24.4 I2C Protocol 24.3 I2C System Configuration Repeated Start Arbitration Procedure SCL1 SCL2 Clock SynchronizationHandshaking Clock Stretching I2ADR Field Descriptions 24.5.1 I2C Address Register I2ADR2describes I2ADR fields I2C Interface Memory Map Divider 24.5.2 I2C Frequency Divider Register I2FDR3describes I2FDRIC I2FDR Field Descriptions IEN Iien 24.5.3 I2C Control Register I2CR4describes I2CR fields I2CR Field Descriptions ICF Iaas IBB IAL SRW IIF 24.5.4 I2C Status Register I2SR5describes I2SR fields I2SR Field Descriptions 24.5.5 I2C Data I/O Register I2DR 24.6 I2C Programming Examples Post-Transfer Software Response Generation of Start I2SR 24.6.4 Generation of Stop Generation of Repeated Start Slave Mode Arbitration Lost Write RXAK=IAAS=1 SRW=1 24-16 Chapter FlexCAN Cantx Canrx RAM MB3 MB2 MB1 MB0 FlexCAN Memory Map 25.1.2 External SignalsFlexCAN Memory Map Typical can system is shown below in Figure Can SystemMessage Buffers Message Buffer Structure Common Fields for Extended and Standard Format Frames Message Buffer Codes for Receive Buffers Common Extended/Standard Format FramesMessage Buffer Codes for Transmit Buffers Extended Format Frames Message Buffer Memory MapFields for Extended Format Frames Fields for Standard Format Frames Message Buffers Functional OverviewIdhigh Idlow Receive Process Transmit Process Self-Received Frames Message Buffer Handling Transmit Message Buffer Deactivation Serial Message Buffers SMBsReceive Message Buffer Deactivation Locking and Releasing Message Buffers Remote Frames Overload Frames Listen-Only ModeTime Stamp Freq Mhz Time-quanta/bit Value + Configuring the FlexCAN Bit TimingBit Timing Examples of System Clock/CAN Bit-Rate/S-Clock FlexCAN Error Counters FlexCAN Initialization Sequence Low-Power Stop Mode for Power Saving Debug ModeSpecial Operating Modes Canmcr Interrupts Auto-Power Save Mode Stop FRZ Halt Notrdy Wakemsk Softrst Frzack Can Module Configuration Register CanmcrProgrammer’s Model 8describes the Canmcr fields Stop Canmcr Field Descriptions 9describes the CANCTRL0 fields FlexCAN Control Register 0 CANCTRL0 11describes the CANCTRL1 fields 10. Transmit Pin ConfigurationTransmit Pin Configuration FlexCAN Control Register 1 CANCTRL1 Samp Prescaler Divide Register Presdiv12describes the Presdiv fields 11. CANCTRL1 Field Descriptions 13. CANCTRL2 Field Descriptions FlexCAN Control Register 2 CANCTRL213describes the CANCTRL2 fields 12. Presdiv Field Descriptions Rx Mask Registers Free Running Timer Timer14describes the Timer fields 14. Timer Field Descriptions 12. Rx Mask Registers RXGMASK, RX14MASK, and RX15MASK Receive Mask Registers RXGMASK, RX14MASK, RX15MASK 17describes the Estat fields FlexCAN Error and Status Register Estat16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions Biterr 17. Estat Field Descriptions BUF10M BUF9M BUF8M Interrupt Mask Register Imask18describes the Imask fields BUF15M BUF14M BUF13M 19. Iflag Field Descriptions Interrupt Flag Register Iflag19describes the Iflag fields 18. Imask Field Descriptions 21describes the Txectr fields FlexCAN Receive Error Counter RxectrFlexCAN Transmit Error Counter Txectr 20describes the Rxectr fields Chapter General Purpose I/O Module MCF5282 Ports Module Block Diagram Modes of Operation FeaturesSdram control Bit DMA timers Uart transmit/receive Overview MCF5282 Ports External Signals External Signal Description UCTS0 ErxerSDA SCL MCF5282 Ports Module Memory Map 31-24 23-16 15-8 AccessMemory Map/Register Definition Register Overview Clre Clrf Clrg Clrh Ddrb DdrcDdreh Ddrel Clra Clrb Clrc Clrd Port Output Data Registers 8-bit Port Output Data Registers PORTn Register Bits Name Description Port Data Direction Registers DDRnPORTn bits are described in Table PORTn 8-bit, 7-bit, 6-bit, and 4-bit Field Descriptions Port Data Direction Register 7-bit 10. Port Pin Data/Set Data Registers 8-bit Port Pin Data/Set Data Registers PORTnP/SETn PORTUAP/SETUA Port Clear Output Data Registers CLRnPORTnP/SETn bits are described in Table PORTnP/SETn 8-bit, 6-bit, and 4-bit Field Descriptions CLRn 8-bit,7-bit, 6-bit, and 4-bit Field Descriptions CLRn register bits are described in Table Port B/C/D Pin Assignment Register Pbcdpar Reset Values for Pbcdpar BitsPort Size Pbpa Reset Pcdpa Reset External Boot Pepar Field Descriptions Port E Pin Assignment Register PeparPEPA3 Single chip mode 10. Reset Values for Pepar Bits and Fields Pfpar controls the pin function of port F75 Port F Pin Assignment Register Pfpar11. Pfpar Field Descriptions Pjpar controls the pin function of port J Port J Pin Assignment Register Pjpar12. Pjpar Field Descriptions Paspar controls the pin function of port AS Port SD Pin Assignment Register PsdparPort AS Pin Assignment Register Paspar Psdpar controls the pin function of port SD 14. Paspar Field Descriptions Port EH/EL Pin Assignment Register Pehlpar ECOL, ERXCLK, ERXDV, ERXD0, Ecrs Port QS Pin Assignment Register PqsparPqspar controls the pin function of port QS 15. Pehlpar Field Descriptions Ptcpar controls the pin function of port TC Port TC Pin Assignment Register PtcparPTCPA3 PTCPA2 PTCPA1 PTCPA0 Ptdpar controls the pin function of port TD Port TD Pin Assignment Register PtdparPTDPA3 PTDPA2 PTDPA1 PTDPA0 Puapar controls the pin function of port UA Port UA Pin Assignment Register Puapar Clkout Input PIN Register PIN Data Port Digital I/O Timing Clkout Output Data Register Output PIN Initialization/Application Information Chapter Queued Analog-to-Digital Converter Qadc Qadc Block Diagram Modes of Operation Debug Mode Port QA Analog Input Signals Port QA Signal Functions Port QA Digital Input/Output Signals Port QB Signal FunctionsPort QB Analog Input Signals Port QB Digital I/O Signals External Trigger Input SignalsMultiplexed Address Output Signals Multiplexed Analog Input Signals Multiplexed Analog Input Channels Voltage Reference SignalsDedicated Analog Supply Signals Dedicated Digital I/O Port Supply Signal This subsection describes the Qadc registers Qadc Module Configuration Register QadcmcrQadc Memory Map Port Data Registers Portqa and Portqb Qadc Test Register Qadctest ANZ ANY ANX ANW Port QA and QB Data Direction Register Ddrqa and Ddrqb Qadc Control Register 0 QACR0 Control RegistersThis subsection describes the Qadc control registers QPR6 Qadc Control Register 0 QACR0 QACR0 Field Descriptions QPR60 Prescaler fSYS Divide-by ValuesDivisor CIE1 PIE1 SSE1 Qadc Control Register 1 QACR1CIE1 Queue 1 Operating Modes Operating Mode Qadc Control Register 2 QACR2 Resume CIE2 PIE2 SSE2 BQ2 QACR2 Field DescriptionsQueue 2 Operating Modes CIE2 MQ2128 Operating Modes Status RegistersQadc Status Register 0 QASR0 This subsection describes the Qadc status registers 27-20 Queued Analog-to-Digital Converter Qadc 27-21 QS9 QS8 CF1 PF1 CF2QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0 CWP Scan Mode Queue Operation PF Asserts?10. QASR0 Field Descriptions 11. CCW Pause Bit Response Queue 1/Queue 2 States 12. Queue Status 12. Queue Status Transition Qadc Status Register 1 QASR1 Conversion Command Word Table CCW IST1 IST0 BYP IST10 Input Sample Times Non-Multiplexed Input Signals Channel NumberPort Signal Name 15. Input Sample Times Right-Justified Unsigned Result Register Rjurr 17. Multiplexed Channel Assignments and Signal DesignationsMultiplexed Input Signals Channel Number Result Registers Result Left-Justified Signed Result Register LjsrrLeft-Justified Unsigned Result Register Ljurr 18. Rjurr Field Descriptions Result Coherency 27.7 Functional DescriptionExternal Multiplexing External Multiplexing Operation 18. External Multiplexing Configuration 21. Analog Input Channels Analog SubsystemModule Version Options Analog-to-Digital Converter Operation Conversion Cycle Times 19. Qadc Analog Subsystem Block Diagram Sample Buffer Channel Decode and Multiplexer Successive Approximation Register SAR Digital Control SubsystemComparator Bias Queue Priority Queue Priority Timing Examples 22. Qadc Queue Operation with Pause Events Queue Priority Schemes22. Trigger Events 23. Status Bits 23. CCW Priority Situation 24. CCW Priority Situation 26. CCW Priority Situation 28. CCW Priority Situation 30. CCW Priority Situation 32. CCW Priority Situation 34. CCW Freeze Situation 38. CCW Freeze Situation Boundary Conditions Single-Scan Modes Disabled ModeReserved Mode Scan Modes Software-Initiated Single-Scan Mode Externally Gated Single-Scan Mode Externally Triggered Single-Scan Mode Interval Timer Single-Scan Mode Continuous-Scan Modes Software-Initiated Continuous-Scan Mode Externally Gated Continuous-Scan Mode Externally Triggered Continuous-Scan Mode Qadc Clock Qclk Generation Periodic Timer Continuous-Scan Mode 42. Qadc Clock Subsystem Functions Periodic/Interval Timer 43illustrates the operation of the queue structure Conversion Command Word Table 43. Qadc Conversion Queue Operation Queued Analog-to-Digital Converter Qadc 27-61 Result Word Table Signal Connection Considerations Analog Power Signals Analog Reference Signals Conversion Timing Schemes 45. Errors Resulting from Clipping 46. External Positive Edge Trigger Mode Timing with Pause 47. Gated Mode, Single Scan Timing 48. Gated Mode, Continuous Scan Timing Analog Supply Filtering and Grounding 49. Star-Ground at the Point of Power Supply Origin Accommodating Positive/Negative Stress Conditions 50. Input Signal Subjected to Negative Stress Iinjp Iinjn Analog Input Considerations 52. External Multiplexing of Analog Signal Sources 53. Electrical Model of an A/D Input Signal Analog Input Pins 24. External Circuit Settling Time to 1/2 LSB Settling Time for the External CircuitSource Resistance RF + Rsrc 100 Ω 10 kΩ 100 kΩ 25. Error Resulting from Input Leakage IOff Error Resulting from LeakageInterrupt Operation PF1 PIE1 Interrupt Sources26. Qadc Status Flags and Interrupt Sources Queue Queue Activity Status Interrupt Flag Chapter Reset Controller Module Name Direction Input Reset Controller Signal PropertiesRsti Rsto Reset Controller Memory Map Reset Control Register RCR Soft WDR POR Reset Status Register RSRLvdf Lvdie WDR RSR Field Descriptions Source Type Reset SourcesPower-On Reset Reset Source Summary Loss-of-Lock Reset External ResetWatchdog Timer Reset Loss-of-Clock Reset Reset Control Flow Reset Control Flow Power-On Reset/Low-Voltage Detect Reset Concurrent ResetsSynchronous Reset Requests Internal Reset Request Reset Status Flags 28-12 Processor/Debug Module Interface Debug module is shown in Figure Debug Module Signals Signal Description Processor Status Encoding Real-Time Trace SupportPST30 Definition Hex PST30 Definition Hex Binary Begin Execution of Taken Branch PST = Ddata Clkout PST CSR AatrAblr Abhr DRc4-0 Register Name Abbreviation Initial State Revision a Shared Debug ResourcesBDM/Breakpoint Registers Rev. a Shared BDM/Breakpoint Hardware TMM Address Attribute Trigger Register Aatr5describes Aatr fields Aatr Field Descriptions Address Breakpoint Registers ABLR, Abhr Address Breakpoint Registers ABLR, Abhr Ablr Field Description Configuration/Status Register CSR6describes Ablr fields 7describes Abhr fields CSR Field Descriptions 8describes CSR fields IPI Data Breakpoint/Mask Registers DBR, Dbmr 9describes DBR fields Program Counter Breakpoint/Mask Registers PBR, Pbmr10describes Dbmr fields 12. PBR Field Descriptions Trigger Definition Register TDR12describes PBR fields 13describes Pbmr fields 14. TDR Field Descriptions 14describes TDR fields Eduu Background Debug Mode BDMCPU Halt Edum 29-17 Clkout Dsclk DSI BDM Serial InterfaceDSO 16describes transmit BDM packet fields Receive Packet FormatTransmit Packet Format 15describes receive BDM packet fields 17. BDM Command Summary BDM Command SetSection Command 18. BDM Field Descriptions ColdFire BDM Command Format18describes BDM fields Extension Words as Required 16. Command Sequence Diagram Command Sequence Diagrams Command Sequence Command Set DescriptionsRead A/D Register RAREG/RDREG Read Memory Location Read Write A/D Register WAREG/WDREG 22. Read Command Sequence 21. Read Command/Result Formats Write Memory Location Write 23. Write Command Format Operands are sent as 16 and 32 bits, respectively Set is returned if a bus error occursDump Memory Block Dump 25. Dump Command/Result Formats Fill Memory Block Fill 26. Dump Command Sequence 28. Fill Command Sequence 27. Fill Command Format No Operation NOP Resume Execution GO Rc encoding Read Control Register Rcreg19. Control Register Map BDM Accesses of the Emac Registers BDM Accesses of the Stack Pointer Registers A7 SSP, USP Write Control Register Wcreg 35. Wcreg Command/Result Formats 20shows the definition of DRc encoding Read Debug Module Register Rdmreg 20. Definition of DRc Encoding-Read Write Debug Module Register WdmregDRc40 Debug Register Definition Mnemonic Initial State Breakpoint Status Real-Time Debug SupportTheory of Operation 21. DDATA30/CSRBSTAT Breakpoint Response Emulator Mode Concurrent BDM and Processor Operation Instruction Operand Syntax 22. PST/DDATA Specification for User-Mode InstructionsProcessor Status, Ddata Definition User Instruction Set 29-41 29-42 23. PST/DDATA Specification for MAC Instructions Supervisor Instruction Set 24. PST/DDATA Specification for Supervisor-Mode Instructions GND PST3 PST2 PST1 PST0 DDATA3 DDATA2 DDATA1 DDATA0 Reset DSIMotorola-Recommended BDM Pinout GND Dsclk 29-46 Chapter Chip Configuration Module CCM Chip Configuration Module Block Diagram Single-Chip Mode Rcon Signal Descriptions30.4.3 D2624, 21, 1916 Reset Configuration Override 1provides an overview of the CCM signals Configuration Read/Write Access Write-Once Bits Read/Write Accessibility BMT Chip Configuration Register CCRFollowing subsection describes the CCM registers Szen Rcsc Reset Configuration Register RconBootps Rcsc Rpllsel Rpllref Boot Port Size Rcsc Chip Select ConfigurationBootps Port Size Configuration Chip Select Configuration Chip Identification Register CIR Reset ConfigurationPIN PRN 10. Configuration During Reset Reset Configuration Pin States During Reset Clock Mode Chip Mode SelectionD2524 11. Chip Configuration Mode Selection Boot Device SelectionOutput Pad Strength Configuration Clock Mode Selection 13. Clock Mode Selection Chip Select ConfigurationCCM does not generate interrupt requests Chapter Ieee 1149.1 Test Access Port Jtag Jtag Block Diagram Pin Function Selected External Signal Description31.3.1 Detailed Signal Description Jtagen Jtag Enable Tclk Test Clock Input 31.3.1.3 TMS/BKPT Test Mode Select / BreakpointTRST/DSCLK Test Reset / Development Serial Clock Signal State to the Disable Module Idcode Register Memory Map/Register DefinitionMemory Map Instruction Shift Register IR Boundary Scan Register Bypass RegisterJtagcfmclkdiv Register Testctrl Register TAP Controller Jtag Module Instruction IR30 Instruction Summary Jtag Instructions5describes public and private instructions Jtag Instructions Idcode Instruction External Test Instruction ExtestSAMPLE/PRELOAD Instruction Highz Instruction Enabletestctrl InstructionLockoutrecovery Instruction Testleakage Instruction Bypass Instruction Initialization/Application InformationRestrictions Clamp Instruction Nonscan Chain Operation Chapter Mechanical Data MCF5282 Pinout 256 Mapbga Pinout Mapbga Pin Pin Functions MCF5282 Signal Description by Pin NumberSecondary Tertiary PF4 PG4PG3 PG2 PQA3 ETRIG1 VRH VDD Vssa VSS PUA1 VDDGPTB0 GPTA0 PQS5 PQA0 MA0 VDD VddaPUA3 VSS Xtal Jtagen GPTB2 Ordering Information Motorola Part Description Speed TemperatureOrderable Part Numbers 32-8 Maximum Ratings Rating Symbol Value UnitAbsolute Maximum Ratings1 HBM Rating Symbol 2lists thermal resistance values Thermal CharacteristicsThermal Characteristics Characteristic Symbol Value Unit Solving equations 1 and 2 for K gives DC Electrical SpecificationsDC Electrical Specifications1 Characteristic Symbol Min Max Unit Wait Doze Stop PLL Electrical Specifications Phase Lock Loop Electrical Specifications Qadc Absolute Maximum Ratings Qadc Electrical CharacteristicsQadc Electrical Specifications Operating Parameter Symbol Min Max Unit IOH = TBD Parameter Symbol Min Num Parameter Symbol Min Max Unit Flash Memory CharacteristicsQadc Conversion Specifications Operating Sgfm Flash Program and Erase Characteristics Sgfm Flash Module Life Characteristics External Interface Timing Characteristics10. Processor Bus Input Timing Specifications Timings listed in -10are shown in Figure Processor Bus Output Timing Specifications11. External Bus Output Timing Specifications Name Characteristic Symbol Min Max Unit Control Outputs Data Outputs Read/Write Internally Terminated Timing Read Bus Cycle Terminated by TA Read Bus Cycle Terminated by TEA Sras Scas Dramw Symbol Min Max Unit 13. Gpio Timing1 33.9 General Purpose I/O TimingSras SCAS1 Dramw 14. Reset and Configuration Override Timing Reset and Configuration Override Timing Clkout Rsti Rsto 33.11 I2C Input/Output Timing Specifications15. I2C Input Timing Specifications between SCL and SDA Num Characteristic Min Max Units 16. I2C Output Timing Specifications between SCL and SDA Fast Ethernet AC Timing Specifications Num Characteristic Min Max Unit MII Receive Signal Timing ERXD30, ERXDV, ERXER, and ErxclkMII Transmit Signal Timing ETXD30, ETXEN, ETXER, Etxclk 17. MII Receive Signal Timing 19. MII Async Inputs Signal Timing MII Async Inputs Signal Timing Ecrs and Ecol19lists MII asynchronous inputs signal timing 18. MII Transmit Signal Timing 20. MII Serial Management Channel Timing MII Serial Management Channel Timing Emdio and Emdc 22lists Qspi timings DMA Timer Module AC Timing SpecificationsQspi Electrical Specifications 21lists timer module AC timings 23. Jtag and Boundary Scan Timing Jtag and Boundary Scan Timing 16. Boundary Scan Jtag Timing 17. Test Access Port Timing 24. Debug AC Timing Specification Debug AC Timing SpecificationsClkout VIL 20. Real-Time Trace AC Timing 20shows real-time trace timing for the values in Table ACR1 Table A-1. CPU Space Register Memory MapAddress Name Mnemonic Size ACR0 Qadc Table A-2. Module Memory Map OverviewAddress Module Size I2C Chip Select Registers Table A-3. Register Memory MapAddress Name Mnemonic Size SCM Registers Sdramc Registers DMA Registers Uart Registers UIP01 UISR1UIMR1 UBG21 I2C Registers DMA Timer RegistersQspi Registers Interrupt Controller Ipsbar + 0xC56 IMRH1 SWACKR0IPRH1 IPRL1 FEC Registers Global Interrupt Acknowledge Cycle Registers Gpio Registers Porttc PortasPortqs Portsd Setb Ipsbar + PortapSeta Ipsbar + Portbp Clras ClraClrf Clrg Edge Port Registers Clock Module Registers Watchdog Timer Registers Qadc Registers General Purpose Timer a Registers General Purpose Timer B Registers FlexCAN Registers Flash Registers MCF5282 User’s Manual Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14 Index-15 Index-16