Motorola MCF5282, MCF5281 user manual Qspiclk, Tck

Overview

Table 14-2. MCF5282 Alphabetical Signal Index (Continued)

	Abbreviation	Function			I/O
QADC analog supply		Supplies positive power to the ESD structures in the QADC			I
		pads.
QSPI_CLK		Provides the serial clock from the QSPI.			O
QSPI_CS[3:0]		Provide QSPI peripheral chip selects.			O
QSPI_DIN		Provides serial data to the QSPI.			I
QSPI_DOUT		Provides serial data from the QSPI.			O
		Indicates the direction of the data transfer on the bus.			I/O
R/W
		Reset configuration select.			I
RCON
		Asserted to enter reset exception processing.			I
RSTI
		Automatically asserted with		Negation indicates that the	O
RSTO			RSTI.
		PLL has regained its lock.
		SDRAM synchronous column address strobe.			O
SCAS
SCKE		SDRAM clock enable.			O
SCL		Clock signal for the I2C interface.			I/O
SDA		Data input/output for the I2C interface.			I/O
		Interface to the chip-select lines of the SDRAMs within a			O
SDRAM_CS[1:0]
		memory block.
SIZ[1:0]		Specify the data access size of the current external bus			O
		reference.
		SDRAM synchronous row address strobe.			O
SRAS
VSTBY		Provides standby voltage to RAM array if VDD is lost.			I
SYNCA/SYNCB		Clear the timer’s clock, providing a means of synchronization			I
		to externally clocked or timed events.
		Indicates that the external data transfer is complete and should			I
TA
		be asserted for one CLKOUT cycle.
		Indicates that an error condition exists for the bus transfer.			I
TEA
TEST		Reserved, should be connected to VSS.			I
TCK		JTAG test logic clock.			I
		Asserted to indicate that a bus transfer is in progress. Negated			O
TIP
		during idle bus cycles.
		Asserted during the first CLKOUT cycle of a transfer when			O
TS
		address and attributes are valid.
		Signals UART that it can begin data transmission.			I
UCTS[1:0]
		Automatic UART request to send outputs.			O
URTS[1:0]
URXD[2:0]		Receiver serial data inputs.			I

14-10 MCF5282 User’s Manual MOTOROLA