Motorola MCF5282, MCF5281 user manual Mmfr Field Descriptions, Bit Name Description

Programming Model

Table 17-17. MMFR Field Descriptions

Bit	Name	Description
31–30	ST	Start of frame delimiter. These bits must be programmed to 01
		for a valid MII management frame.
29–28	OP	Operation code. This field must be programmed to 10 (read) or
		01 (write) to generate a valid MII management frame. A value
		of 11 will produce “read” frame operation while a value of 00 will
		produce “write” frame operation, but these frames will not be MII
		compliant.
27–23	PA	PHY address. This field specifies one of up to 32 attached PHY
		devices.
22–18	RA	Register address. This field specifies one of up to 32 registers
		within the specified PHY device.
17–16	TA	Turn around. This field must be programmed to 10 to generate
		a valid MII management frame.
15–0	DATA	Management frame data. This is the field for data to be written
		to or read from the PHY register.

To perform a read or write operation on the MII Management Interface, the MMFR register must be written by the user. To generate a valid read or write management frame, the ST field must be written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame will be generated but will not comply with the IEEE 802.3 MII definition.

To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time the contents of the MMFR register will be altered as the contents are serially shifted and will be unpredictable if read by the user. Once the write management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR register will match the original value written.

To generate an MII Management Interface read frame (read a PHY register) the user must write {01 10 PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time the contents of the MMFR register will be altered as the contents are serially shifted, and will be unpredictable if read by the user. Once the read management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR register will match the original value written except for the DATA field whose contents have been replaced by the value read from the PHY register.

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