Motorola MCF5281, MCF5282 user manual Estat Field Descriptions, Biterr

			Programmer’s Model
			Table 25-17. ESTAT Field Descriptions
Bits	Name		Description
15–14	BITERR	Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
		00 No transmit bit error
		01 At least one bit sent as dominant was received as recessive
		10 At least one bit sent as recessive was received as dominant
		11 Reserved
		NOTE: The transmit bit error field is not modified during the arbitration field or the ACK slot
		bit time of a message, or by a transmitter that detects dominant bits while sending a passive
		error frame.
13	ACKERR	Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been
		correctly received for a transmitted message.
		0	No ACK error was detected since the last read of this register.
		1	An ACK error was detected since the last read of this register.
12	CRCERR	Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the last
		transmitted or received message was valid.
		0	No CRC error was detected since the last read of this register.
		1	A CRC error was detected since the last read of this register.
11	FORMERR	Message format error. The FORMERR bit indicates whether or not the message format of the
		last transmitted or received message was correct.
		0	No format error was detected since the last read of this register.
		1	A format error was detected since the last read of this register.
10	STUFERR	Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in the
		last transmitted or received message was correct.
		0	No bit stuffing error was detected since the last read of this register.
		1	A bit stuffing error was detected since the last read of this register.
9	TXWARN	Transmit error status flag. The TXWARN status flag reflects the status of the FlexCAN
		transmit error counter.
		0	Transmit error counter < 96.
		1	Transmit error counter ≥ 96.
8	RXWARN	Receiver error status flag. The RXWARN status flag reflects the status of the FlexCAN
		receive error counter.
		0	Receive error counter < 96.
		1	Receive error counter ≥ 96.
7	IDLE	Idle status. The IDLE bit indicates when there is activity on the CAN bus.
		0	The CAN bus is not idle.
		1	The CAN bus is idle.
6	TX/RX	Transmit/receive status. The TX/RX bit indicates when the FlexCAN module is transmitting
		or receiving a message. TX/RX has no meaning when IDLE = 1.
		0	The FlexCAN is receiving a message if IDLE = 0.
		1	The FlexCAN is transmitting a message if IDLE = 0.
5–4	FCS	Fault confinement state. The FCS[1:0] field describes the state of the FlexCAN. If the
		SOFTRST bit in CANMCR is asserted while the FlexCAN is in the bus off state, the error and
		status register is reset, including FCS[1:0]. However, as soon as the FlexCAN exits reset,
		FCS[1:0] bits will again reflect the bus off state. Refer to Section 25.5.11, “FlexCAN Receive
		Error Counter (RXECTR)” for more information on entry into and exit from the various fault
		confinement states.
		00 Error active
		01 Error passive
		1X Reserved

MOTOROLA Chapter 25. FlexCAN 25-29