Motorola MCF5281 Processor Bus Output Timing Specifications, 10lists processor bus output timings

Processor Bus Output Timing Specifications

Timings listed in Table 33-10are shown in Figure 33-1.

* The timings are also valid for inputs sampled on the negative clock edge.

CLKOUT(66.67 MHz)				1.5V
		T	SETUP
				THOLD
Input Setup And Hold		1.5V Valid 1.5V
	Invalid				Invalid

Vh = VIH

Input Rise Time

Vl = VIL

Vh = VIH

Input Fall Time

Vl = VIL

trise = 1.5 ns

tfall = 1.5 ns

CLKOUTB4

B5

Inputs

Figure 33-1. General Input Timing Requirements

33.8 Processor Bus Output Timing Specifications

Table 33-10lists processor bus output timings.

Table 33-11. External Bus Output Timing Specifications

Name	Characteristic				Symbol	Min		Max		Unit
				Control Outputs
B6a	CLKOUT high to chip selects valid 1				t	—	0.5t	CYC	+10	ns
					CHCV
B6b	CLKOUT high to byte enables				tCHBV	—	0.5tCYC +10			ns
		(BS[3:0]) valid2
B6c	CLKOUT high to output enable			valid3	tCHOV	—	0.5tCYC +10			ns
			(OE)
B7	CLKOUT high to control output				tCHCOI	0.5tCYC + 2		—		ns
			(BS[3:0], OE) invalid
B7a	CLKOUT high to chip selects invalid				tCHCI	0.5tCYC + 2		—		ns

MOTOROLA Chapter 33. Electrical Characteristics 33-11