Motorola MCF5281 user manual MCF5282 Key Features

MCF5282 Key Features

•Phase locked loop (PLL)

—Crystal or external oscillator reference

—2- to 10-MHz reference frequency for normal PLL mode

—33- to 66-MHz oscillator reference frequency for 1:1 mode

—Low-power modes supported

—Separate clock output pin

•Two interrupt controllers

—Support for up to 63 interrupt sources per interrupt controller (a total of 126), organized as follows:

–56 fully-programmable interrupt sources

–7 fixed-level interrupt sources

—Seven external interrupt signals

—Unique vector number for each interrupt source

—Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

—Support for hardware and software interrupt acknowledge (IACK) cycles

—Combinatorial path to provide wake-up from low-power modes

•DMA controller

—Four fully programmable channels

—Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers

—Source/destination address pointers that can increment or remain constant

—24-bit byte transfer counter per channel

—Auto-alignment transfers supported for efficient block movement

—Bursting and cycle steal support

—Software-programmable connections between the 11 DMA requesters in the UARTs (3), 32-bit timers (4) plus external logic (4) and the four DMA channels

•External bus interface

—Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)

—SDRAM controller supports 8-, 16-, and 32-bit wide memory devices

—Glueless interface to SRAM devices with or without byte strobe inputs

—Programmable wait state generator

—32-bit bidirectional data bus

—24-bit address bus

MOTOROLA Chapter 1. Overview 1-5