Motorola MCF5281, MCF5282 user manual Synsr Field Descriptions, Locks

			Memory Map and Registers
		Table 9-5. SYNSR Field Descriptions
Bit(s)	Name		Description
7	PLLMODE	Clock mode bit. The PLLMODE bit is configured at reset and reflects the clock mode
		as shown in Table 9-6.
		1	PLL clock mode
		0	External clock mode
6	PLLSEL	PLL select. Configured at reset and reflects the PLL mode as shown in Table 9-6.
		1	Normal PLL mode
		0	1:1 PLL mode
5	PLLREF	PLL reference. Configured at reset and reflects the PLL reference source in normal
		PLL mode as shown in Table 9-6.
		1	Crystal clock reference
		0	External clock reference
4	LOCKS	Sticky indication of PLL lock status.
		1	No unintentional PLL loss of lock since last system reset or MFD change
		0	PLL loss of lock since last system reset or MFD change or currently not locked due
			to exit from STOP with FWKUP set
		The lock detect function sets the LOCKS bit when the PLL achieves lock after:
		•	A system reset
		•	A write to SYNCR that changes the MFD[2:0] bits
		When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains
		cleared until one of the two listed events occurs.
		In stop mode, if the PLL is intentionally disabled, then the LOCKS bit reflects the value
		prior to entering stop mode. However, if FWKUP is set, then LOCKS is cleared until
		the PLL regains lock. Once lock is regained, the LOCKS bit reflects the value prior to
		entering stop mode. Furthermore, reading the LOCKS bit at the same time that the PLL
		loses lock does not return the current loss of lock condition.
		In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and
		1:1 PLL mode, LOCKS is set after reset.
3	LOCK	Set when the PLL is locked. PLL lock occurs when the synthesized frequency is within
		approximately 0.75 percent of the programmed frequency. The PLL loses lock when a
		frequency deviation of greater than approximately 1.5 percent occurs. Reading the
		LOCK flag at the same time that the PLL loses lock or acquires lock does not return
		the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a
		condition for releasing reset.
		If operating in external clock mode, LOCK remains cleared after reset.
		1	PLL locked
		0	PLL not locked

MOTOROLA Chapter 9. Clock Module 9-9