Motorola MCF5281, MCF5282 Line Transfers, Line Read Bus Cycles, Allowable Line Access Patterns

Data Transfer Operation

CSCRn[BSTR,BSTW]. A line access to a burst-inhibited region first accesses the MCF5282 bus encoded as a line access. The SIZ[1:0] encoding does not exceed the programmed port size. The address changes if internal termination is used but does not change if external termination is used, as shown in Figure 13-12and Figure 13-13.

13.4.7.1 Line Transfers

Aline is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address boundaries. Table 13-4shows allowable patterns for line accesses.

Table 13-4. Allowable Line Access Patterns

A[3:2]	Longword Accesses
00	0–4–8–C
01	4–8–C–0
10	8–C–0–4
11	C–0–4–8

13.4.7.2 Line Read Bus Cycles

Figure 13-12and Figure 13-13show a line access read with zero wait states. The access starts like a basic read bus cycle with the first data transfer sampled on the rising edge of S4, but the next pipelined burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined data burst is single cycle until the last one, which can be held for up to two CLKOUT cycles after TA is asserted. Note that CSn are asserted throughout the burst transfer. This example shows the timing for external termination, which differs from the internal termination example in Figure 13-13only in that the address lines change only at the beginning (assertion of TS and TIP) and end (negation of TIP) of the transfer.

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12 S13

CLKOUT

A[31:0], SIZ[1:0]

R/W

TIP

TS

CSn, BSn, OE

D[31:0]

Read

Read

Read

TA

Figure 13-12. Line Read Burst (2-1-1-1), External Termination

MOTOROLA Chapter 13. External Interface Module (EIM) 13-11