Motorola MCF5282 Qspi Wrap Register QWR, 5gives Qdlyr field descriptions, QWR Field Descriptions

Programming Model

Table 22-5gives QDLYR field descriptions.

Table 22-5. QDLYR Field Descriptions

Bits

Name

Description

15

SPE

QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command

RAM. Automatically cleared by the QSPI when a transfer completes. The user can also clear this bit to abort

transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].

14–8

QCD

QSPICLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay

from assertion of the chip selects to valid QSPI_CLK transition.

7–0

DTL

Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay

after the serial transfer.

22.5.3 QSPI Wrap Register (QWR)

15

14

13

12

11

8

7

4

3

0

Field

HALT

WREN

WRTO

CSIV

ENDQP

CPTQP

NEWQP

Reset

0000_0000_0000_0000

R/W

R/W

R

R/W

Address

IPSBAR + 0x348

Figure 22-6. QSPI Wrap Register (QWR)

Table 22-6gives QWR field descriptions.

			Table 22-6. QWR Field Descriptions
Bits	Name		Description
15	HALT	Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has completed
		execution of the current command.
14	WREN	Wraparound enable. Enables wraparound mode.
		0	Execution stops after executing the command pointed to by QWR[ENDQP].
		1	After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed
			to by QWR[NEWQP] and continue execution.
13	WRTO	Wraparound location. Determines where the QSPI wraps to in wraparound mode.
		0	Wrap to RAM entry zero.
		1	Wrap to RAM entry pointed to by QWR[NEWQP].
12	CSIV	QSPI_CS inactive level.
		0	QSPI chip select outputs return to zero when not driven from the value in the current command RAM
			entry during a transfer (that is, inactive state is 0, chip selects are active high).
		1	QSPI chip select outputs return to one when not driven from the value in the current command RAM
			entry during a transfer (that is, inactive state is 1, chip selects are active low).
11–8	ENDQP	End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
7–4	CPTQP	Completed queue entry pointer. Points to the RAM entry that contains the last command to have been
		completed. This field is read only.
3–0	NEWQP	Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a
		transfer.

22-12 MCF5282 User’s Manual MOTOROLA