Processor Bus Output Timing Specifications

Figure 33-5shows an SDRAM read cycle.

CLKOUT

D1

A[23:0]

SRAS

SCAS 1

DRAMW

D[31:0]

SDRAM_CS[1:0]

BS[3:0]

0

1

 

2

 

 

3

 

4

5

 

6

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D3

Row

D4

D2

D4

8

9

10

11

12

13

 

 

 

 

 

 

 

Column

D5

D6

D4

ACTV

NOP

READ

NOP

PRE

1DACR[CASL] = 2

Figure 33-5. SDRAM Read Cycle

Table 33-12. SDRAM Timing

NUM

Characteristic1

Symbol

Min

Max

Unit

D1

CLKOUT high to SDRAM address valid

tCHDAV

10

ns

D2

CLKOUT high to SDRAM control valid

tCHDCV

10

ns

D3

CLKOUT high to SDRAM address invalid

tCHDAI

2

ns

D4

CLKOUT high to SDRAM control invalid

tCHDCI

2

ns

D5

SDRAM data valid to CLKOUT high

tDDVCH

6

ns

D6

CLKOUT high to SDRAM data invalid

tCHDDI

1

ns

D72

CLKOUT high to SDRAM data valid

tCHDDVW

10

ns

D82

CLKOUT high to SDRAM data invalid

tCHDDIW

2

ns

1All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.

2D7 and D8 are for write cycles only.

33-16

MCF5282 User’s Manual

MOTOROLA

Page 766
Image 766
Motorola MCF5282, MCF5281 user manual Sras Scas Dramw, Symbol Min Max Unit