Motorola MCF5281, MCF5282 Chip Select Mask Registers CSMR0-CSMR6, 7describes Csmr fields, Bam

			Chip Select Registers
		Table 12-6. CSARn Field Description
Bits	Name	Description
15–0	BA	Base address. Defines the base address for memory dedicated to chip select
			CS[6:0]. BA is compared
		to bits 31–16 on the internal address bus to determine if chip select memory is being accessed.

12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6)

The CSMRs, Figure 12-3,are used to specify the address mask and allowable access types for the respective chip selects.

.

31	16	15	9	8	7		6	5		4	3	2	1	0
Field	BAM	—		WP	—	AM		C/I	SC		SD	UC	UD	V
Reset		Unitialized												0
R/W		R/W
Addr	0x084 (CSMR0); 0x090 (CSMR1); 0x09C (CSMR2); 0x0A8 (CSMR3);
	0x0B4 (CSMR4); 0x0C0 (CSMR5); 0x0CC (CSMR6)

Figure 12-3. Chip Select Mask Registers (CSMRn)

Table 12-7describes CSMR fields.

				Table 12-7. CSMRn Field Descriptions
Bits	Name				Description
31–16	BAM	Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes
		the corresponding CSAR bit to be ignored in the decode.
		0	Corresponding address bit is used in chip select decode.
		1 Corresponding address bit is a don’t care in chip select decode.
		The block size for CS[6:0] is 2n where n = (number of bits set in respective CSMR[BAM]) + 16.
		So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008, CS0 addresses a 128-Kbyte (217 byte) range
		from 0x0000–0x1_FFFF.
		Likewise, for		CS0	to access 32 Mbytes (225 bytes) of address space starting at location 0x0000, and
		for CS1 to access 16 Mbytes (224 bytes) of address space starting after the CS0 space, then CSAR0
		= 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] = 0x00FF.
8	WP	Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting
		to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip select
		not being selected. No exception occurs.
		0	Both read and write accesses are allowed.
		1	Only read accesses are allowed.
7	—	Reserved, should be cleared.
6	AM	Alternate master. When AM = 0 during a DMA access, SC, SD, UC, and UD are don’t cares in the
		chip select decode.

MOTOROLA Chapter 12. Chip Select Module 12-7