Motorola MCF5282, MCF5281 user manual Message Buffer Handling, Self-Received Frames

Functional Overview

the MB, the ID field, data field (8 bytes at most) and the LENGTH field are stored, the Code field is updated and a status flag is set in the IFLAG register.

The CPU should read a receive frame from its MB in the following way:

•Control/status word (mandatory—activates internal lock for this buffer).

•ID (Optional—needed only if a mask was used).

•Data field word(s).

•Free-running timer (Releases internal lock —optional).

The read of the free-running timer is not mandatory. If not executed, the MB remains locked, unless the CPU starts the read process for another MB. Note that only a single MB is locked at a time. The only mandatory CPU read operation is of the Control/Status word, to assure data coherency. If the BUSY bit is set in the MB code, then the CPU should defer until this bit is negated.

The CPU should synchronize to frame reception by the status flag for the specific MB (see Section 25.5.10, “Interrupt Flag Register (IFLAG)”), and not by the control/status word code field for that MB. This is because polling the control/status word may lock the MB (see above), and the Code may change before the full frame is received into the MB.

Note that the received identifier field is always stored in the matching MB, thus the contents of the identifier field in a MB may change if the match was due to mask.

25.4.2.1 Self-Received Frames

The FlexCAN receives self-transmitted frames if there exists a matching receive MB.

25.4.3 Message Buffer Handling

In order to maintain data coherency and proper FlexCAN operation, the CPU must obey the rules listed in Section 25.4.1, “Transmit Process” and in Section 25.4.2, “Receive Process.” Deactivation of a message buffer (MB) is a host action that causes that message buffer to be excluded from FlexCAN transmit or receive processes. Any CPU write access to a control/status word of MB structure deactivates that MB, thus excluding it from Rx/Tx processes. Any form of CPU MB structure access within the FlexCAN (other than those specified in Section 25.4.1, “Transmit Process” and in Section 25.4.2, “Receive Process”) may cause the FlexCAN to behave in an unpredictable manner.

The match/arbitration processes are performed only during one period by the FlexCAN. Once a winner or match is determined, there is no re-evaluation whatsoever, in order to ensure that a receive frame is not lost. Two receive MBs or more that hold a matching ID to a received frame do not assure reception in the FlexCAN if the user has deactivated the matching MB after FlexCAN has scanned the second.

25-10 MCF5282 User’s Manual MOTOROLA