Motorola MCF5281, MCF5282 user manual Cache Operation, Interaction with Other Modules

Cache Operation

31	Local Address Bus		4	3 21 0	31			4
		10
						I
							or D Line	Buffer
								Address

=

Fill Hit

31 11

0

TAG VALID

128

=

Tag Hit

External Data[31:0]

I or D Line Buffer Storage

MUX

31 0

0

DATA

‘512

MUX

Local Data Bus

Figure 4-1. Cache Block Diagram

4.3Cache Operation

The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's memory references appear as supervisor data accesses but the unit can be programmed to generate user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner.

4.3.1Interaction with Other Modules

Because both the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing.

If the referenced address is mapped into the SRAM module, that module will service the request in a single cycle. In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion.

MOTOROLA Chapter 4. Cache 4-3