Motorola MCF5281, MCF5282 user manual Termination, Bandwidth Control

DMA Controller Module Functional Description

16.5.4.2Bandwidth Control

Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCRn[AA] = 1, the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated.

If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus. See Section 8.5.3, “Bus Master Park Register (MPARK).”

16.5.5 Termination

An unsuccessful transfer can terminate for one of the following reasons:

•Error conditions—When the MCF5282 encounters a read or write cycle that terminates with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding register is lost.

•Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal. The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits.

MOTOROLA Chapter 16. DMA Controller Module 16-15