Motorola MCF5282, MCF5281 Chip Select Configuration, CCM does not generate interrupt requests

Reset

Table 30-13. Clock Mode Selection 1

Clock Mode		Synthesizer Status Register (SYNSR)
	PLLSEL Bit		PLLREF Bit	PLLMOD
External clock mode; PLL disabled	0		0	0
1:1 PLL mode	0		0	1
Normal PLL mode; external clock reference	1		0	1
Normal PLL mode; crystal oscillator reference	1		1	1

1Modifying the default configurations is possible only if the external RCON pin is asserted low.

30.6.6 Chip Select Configuration

The chip select configuration (CS[6:4]) is selected during reset and reflected in the RCSC field of the CCR. Once reset is exited, the chip select configuration cannot be changed. Table 30-10shows the different chip select configurations that can be implemented during reset configuration.

30.7 Reset

Reset initializes CCM registers to a known startup state as described in Section 30.5, “Memory Map and Registers.” The CCM controls chip configuration at reset as described in Section 30.6, “Functional Description.”

30.8 Interrupts

The CCM does not generate interrupt requests.

30-12 MCF5282 User’s Manual MOTOROLA