Motorola MCF5282, MCF5281 Rsti, Rsto, Reset Controller Signal Properties, Name Direction Input

Block Diagram

28.2 Block Diagram

Figure 28-1illustrates the reset controller and is explained in the following sections.

RSTI

Pin

Power-On

Reset

Watchdog

Timer Timeout

PLL

Loss of Clock

PLL

Loss of Lock

Software

Reset

LVD

Detect

Reset

Controller

RSTO

Pin

To Internal Resets

Figure 28-1. Reset Controller Block Diagram

28.3 Signals

Table 28-1provides a summary of the reset controller signal properties. The signals are described in the following paragraphs.

Table 28-1. Reset Controller Signal Properties

	Name	Direction	Input	Input
			Hysteresis	Synchronization
		I	Y	Y 1
RSTI
		O	—	—
RSTO

1RSTI is always synchronized except when in low-power stop mode.

28.3.1RSTI

Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset request to be recognized and latched.

28.3.2RSTO

This active-low output signal is driven low when the internal reset controller module resets the chip. When RSTO is active, the user can drive override options on the data bus.

28-2 MCF5282 User’s Manual MOTOROLA