Motorola MCF5282, MCF5281 user manual Background Debug Mode BDM, CPU Halt, Edum, Eduu

Background Debug Mode (BDM)

			Table 29-14. TDR Field Descriptions (continued)
Bits	Name		Description
28–22/	EDx	Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on
12–6		the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
28/12		EDLW	Data longword. Entire processor’s local data bus.
27/11		EDWL	Lower data word.
26/10		EDWU	Upper data word.
25/9		EDLL	Lower lower data byte. Low-order byte of the low-order word.
24/8		EDLM	Lower middle data byte. High-order byte of the low-order word.
23/7		EDUM	Upper middle data byte. Low-order byte of the high-order word.
22/6		EDUU	Upper upper data byte. High-order byte of the high-order word.
21/5	DI	Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This
		can develop a trigger based on the occurrence of a data value other than the DBR contents.
20–18/	EAx	Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all three bits
4–2		disables the breakpoint.
20/4		EAI	Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and
			ABHR.
19/3		EAR	Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR
			and ABHR.
18/2		EAL	Enable address breakpoint low. The breakpoint is based on the address in the ABLR.
17/1	EPC	Enable PC breakpoint. If set, this bit enables the PC breakpoint.
16/0	PCI	Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR and PBMR to
		enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and PBMR.

29.5 Background Debug Mode (BDM)

The ColdFire Family implements a low-level system debugger in the microprocessor hardware. Communication with the development system is handled through a dedicated, high-speed serial command interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module. Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running.

29.5.1 CPU Halt

Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority:

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