Motorola MCF5282, MCF5281 user manual Data Transfer Modes, Dual-Address Transfers

DMA Controller Module Functional Description

external request is initiated by asserting DREQn while DCRn[EEXT] is set. Note that multiple transfers will occur if DREQn is continuously asserted.

•Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA continuously transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until DSRn[DONE] is set. If BCRn is a multiple of BWC, the DMA request signal is negated until the bus cycle terminates to allow the internal arbiter to switch masters. DCRn[BWC] = 000 specifies the maximum transfer rate; other values specify a transfer rate limit.

The DMA performs the specified number of transfers, then relinquishes bus control. The DMA negates its internal bus request on the last transfer before BCRn reaches a multiple of the boundary specified in BWC. On completion, the DMA reasserts its bus request to regain mastership at the earliest opportunity. The DMA loses bus control for a minimum of one bus cycle.

16.5.2 Data Transfer Modes

Each channel supports dual-address transfers, described in the next section.

16.5.2.1Dual-Address Transfers

Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA request. If no error condition exists, DSRn[REQ] is set.

•Dual-address read—The DMA controller drives the SARn value onto the internal address bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is larger than the source), the DMA initiates the write portion of the transfer.

If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.

•Dual-address write—The DMA controller drives the DARn value onto the address bus. If DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the completion of a successful write cycle. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated. If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters.

If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.

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