INDEX

A

A/D converter bias, 27-37

block diagram, 27-35channel decode, 27-36comparator, 27-37cycle times, 27-35multiplexer, 27-36operation, 27-34sample buffer, 27-36state machine, 27-37

successive approximation register (SAR), 27-37Access error

on operand reads, 2-13on operand writes, 2-14

Acknowledge error (ACKERR), 25-29Address error exception, 2-14Address variant, 29-4

Analog inputs, 27-73Analog power signals, 27-63Analog reference signals, 27-63Analog supply

filtering, 27-67grounding, 27-67

Async inputs signal timing, 33-22Automatic echo, 23-25

B

Baud rate calculating, 23-19selection, 22-6

BDM

see debug commands

DUMP, 29-27

FILL, 29-29format, 29-21GO, 29-31NOP, 29-31RAREG/RDREG, 29-23RCREG, 29-32RDMREG, 29-35READ, 29-24sequence diagrams, 29-22summary, 29-20WAREG/WDREG, 29-24WCREG, 29-34

WDMREG, 29-36WRITE, 29-26

CPU halt, 29-16

operation with processor, 29-39packet format

receive, 29-19transmit, 29-19

recommended pinout, 29-46register accesses

EMAC, 29-33stack pointer, 29-33

serial interface, 29-18timing diagrams

BDM serial port AC timing, 33-28real-time trace AC timing, 33-28

Bit error (BITERR), 25-29

Bit reverse register (BITREV) instruction, 2-29Bit stuff error (STUFFERR), 25-29

Branch instruction execution timing, 2-28Buffer descriptors

receive (RxBD), 17-47driver/DMA operation, 17-46

Bus

access by matches in CSCR and DACR, 13-4characteristics, 13-2

data transfer back-to-back cycles, 13-10burst cycles, 13-10

allowable line access patterns, 13-11line read bus cycles, 13-11

line transfers, 13-11

line write bus cycles, 13-13cycle execution, 13-3

cycle states, 13-5

fast termination cycle, 13-9read cycle, 13-6

write cycle, 13-8electrical characteristics

input timing specifications, 33-10output timing specifications, 33-11

features, 13-1internal

arbitration, 8-9algorithms, 8-11fixed mode, 8-12overview, 8-11round-robin mode, 8-11

MPARK, 8-12

MOTOROLA

MCF5282 User’s Manual

Index-1

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Image 801
Motorola MCF5281, MCF5282 user manual Index