Motorola MCF5281, MCF5282 user manual Sdram Controller Signals

MCF5282 External Signals

port size and burst-capability indication, wait-state generation, and internal/external termination.

Reset clears all chip select programming; CS0 is the only chip select initialized out of reset. CS0 is also unique because it can function at reset as a global chip select that allows boot ROM to be selected at any defined address space. The port size for boot CS0 is set during chip configuration by the levels on D[19:18] on the rising edge of RSTI, as described in Chapter 30, “Chip Configuration Module (CCM).” The chip-select implementation is described in Chapter 12, “Chip Select Module.”

These pins can also be configured as A[23:21] and GPIO PJ[3:0].

14.2.2 SDRAM Controller Signals

These signals are used for SDRAM accesses.

14.2.2.1SDRAM Row Address Strobe (SRAS)

This output is the SDRAM synchronous row address strobe. This pin is configured as GPIO PSD5 in single-chip mode.

14.2.2.2SDRAM Column Address Strobe (SCAS)

This output is the SDRAM synchronous column address strobe. This pin is configured as GPIO PSD4 in single-chip mode.

14.2.2.3SDRAM Write Enable (DRAMW)

The DRAM write signal (DRAMW) is asserted to signify that a DRAM write cycle is underway. A read cycle is indicated by the negation of DRAMW.

This pin is configured as GPIO PSD3 in single-chip mode.

14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0])

These signals interface to the chip-select lines of the SDRAMs within a memory block. Thus, there is one SDRAM_CS line for each memory block (the MCF5282 supports two SDRAM memory blocks).

These pins is configured as GPIO PSD[2:1] in single-chip mode.

14.2.2.5SDRAM Clock Enable (SCKE)

This output is the SDRAM clock enable.

This pin is configured as GPIO PSD0 in single-chip mode.

MOTOROLA Chapter 14. Signal Descriptions 14-21