Motorola MCF5281, MCF5282 user manual Clock Operation During Reset, System Clock Generation

Functional Description

Table 9-7. Clock Out and Clock In Relationships

System Clock Mode	PLL Options 1
Normal PLL clock mode	fsys = fref ⋅ 2(MFD + 2)/2RFD
1:1 PLL clock mode	fsys = fref
External clock mode	fsys = fref

1fref = input reference frequency fsys = CLKOUT frequency MFD ranges from 0 to 7.

RFD ranges from 0 to 7.

CAUTION

XTAL must be tied low in external clock mode when reset is asserted. If it is not, clocks could be suspended indefinitely.

The external clock is divided by two internally to produce the system clocks.

9.7.2Clock Operation During Reset

In external clock mode, the system is static and does not recognize reset until a clock is applied to EXTAL.

In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock to the PLL begins operating within the limits given in the electrical specifications.

If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system clock source changes to the PLL operating in SCM. If SCM is not functional, the system becomes static. Alternately, if the LOCEN bit in SYNCR is cleared when the PLL fails, the system becomes static. If external reset is asserted, the system cannot enter reset unless the PLL is capable of operating in SCM.

9.7.3System Clock Generation

In normal PLL clock mode, the default system frequency is two times the reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency multiplier.

When programming the PLL, do not exceed the maximum system clock frequency listed in the electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs when the MFD bits are changed:

1.Determine the appropriate value for the MFD and RFD fields in the SYNCR. The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an RFD factor to provide the required frequency.

2.Write a value of RFD (from step 1) + 1 to the RFD field of the SYNCR.

MOTOROLA Chapter 9. Clock Module 9-11