Motorola MCF5282, MCF5281 user manual Back-to-Back Bus Cycles, Burst Cycles

Data Transfer Operation

13.4.6 Back-to-Back Bus Cycles

The MCF5282 runs back-to-back bus cycles whenever possible. For example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle. Figure 13-11shows a read back-to-back with a write.

S0	S1	S2	S3	S4	S5	S0	S1	S2	S3	S4	S5
CLKOUT
A[31:0], SIZ[1:0]
R/W
TIP
TS
CSn, BSn
OE
D[31:0]			Read					Write
TA

Figure 13-11. Back-to-Back Bus Cycles

Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable.

13.4.7 Burst Cycles

The MCF5282 can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst cycle. A line transfer to a 32-bit port would take a 4-longword burst cycle.

The MCF5282 bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize DMA transfers. A user can add wait states by delaying termination of the cycle. The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller port sizes, SIZ[1:0] indicates the size of the entire transfer. For example, if the MCF5282 writes a longword to an 8-bit port, SIZ[1:0] = 00 for the first byte transfer and does not change.

The CSCRs can be used to enable bursting for reads, writes, or both. MCF5282 memory space can be declared burst-inhibited for reads and writes by clearing the appropriate

13-10 MCF5282 User’s Manual MOTOROLA