Programming Model

17.5.4.9 Receive Control Register (RCR)

The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time).

Field

Reset

R/W

31

27

26

16

 

 

MAX_FL

 

 

 

 

0000_0101_1110_1110

R/W

15

6

5

4

3

2

1

0

Field

Reset

R/W Address

FCE

BC_REJ

PROM

MII_MODE

DRT

LOOP

 

 

 

 

 

 

 

0000_0000_0000_0001

R/W

IPSBAR + 0x1084

Figure 17-12. Receive Control Register (RCR)

Table 17-21. RCR Field Descriptions

Bits

Name

Description

 

 

 

31–27

Reserved, should be cleared.

 

 

 

26–16

MAX_FL

Maximum frame length. Resets to decimal 1518. Length is

 

 

measured starting at DA and includes the CRC at the end of

 

 

the frame. Transmit frames longer than MAX_FL will cause

 

 

the BABT interrupt to occur. Receive Frames longer than

 

 

MAX_FL will cause the BABR interrupt to occur and will set

 

 

the LG bit in the end of frame receive buffer descriptor. The

 

 

recommended default value to be programmed by the user is

 

 

1518 or 1522 (if VLAN Tags are supported).

 

 

 

15–6

Reserved, should be cleared.

 

 

 

5

FCE

Flow control enable. If asserted, the receiver will detect

 

 

PAUSE frames. Upon PAUSE frame detection, the

 

 

transmitter will stop transmitting data frames for a given

 

 

duration.

 

 

 

4

BC_REJ

Broadcast frame reject. If asserted, frames with DA

 

 

(destination address) = FF_FF_FF_FF_FF_FF will be

 

 

rejected unless the PROM bit is set. If both BC_REJ and

 

 

PROM = 1, then frames with broadcast DA will be accepted

 

 

and the M (MISS) bit will be set in the receive buffer

 

 

descriptor.

 

 

 

3

PROM

Promiscuous mode. All frames are accepted regardless of

 

 

address matching.

 

 

 

2

MII_MODE

Media independent interface mode. Selects external

 

 

interface mode. Setting this bit to one selects MII mode,

 

 

setting this bit equal to zero selects 7-wire mode (used only

 

 

for serial 10 Mbps). This bit controls the interface mode for

 

 

both transmit and receive blocks.

 

 

 

MOTOROLA

Chapter 17. Fast Ethernet Controller (FEC)

17-33

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Motorola MCF5281, MCF5282 user manual Receive Control Register RCR, Maxfl, FCE Bcrej Prom Miimode DRT Loop, Fce