Motorola MCF5282, MCF5281 user manual Sram Base Address Register Rambar, PRI1 PRI2 SPV, PRI1, PRI2

Models: MCF5282 MCF5281

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SRAM Programming Model

5.3.1SRAM Base Address Register (RAMBAR)

The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module.

The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register.

The RAMBAR can be read or written from the debug module in a similar manner.

All undefined bits in the register are reserved. These bits are ignored during writes to the RAMBAR, and return zeroes when read from the debug module.

The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are unaffected.

The RAMBAR contains several control fields. These fields are shown in Figure 5-1

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Field

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

Undefined

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

Reset

R/W Address

15

14

13

12

11

10

9

8

 

7

6

5

4

3

2

1

0

 

 

 

PRI1

PRI2

SPV

 

WP

 

 

C/I

SC

SD

UC

UD

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Undefined

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU + 0xC05

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5-1. SRAM Base Address Register (RAMBAR)

Table 5-1. SRAM Base Address Register

Bits

Name

Description

 

 

 

31–16

BA

Base address. Defines the 0-modulo-64K base address of the SRAM module. By

 

 

programming this field, the SRAM may be located on any 64-Kbyte boundary within the

 

 

processor’s 4-Gbyte address space.

15–12

Reserved, should be cleared.

 

 

 

11–10

PRI1, PRI2

Priority bit. PRI1 determines if DMA or CPU has priority in upper 32k bank of memory. PRI2

 

 

determines if DMA or CPU has priority in lower 32k bank of memory. If bit is set, DMA has

 

 

priority. If bit is reset, CPU has priority. Priority is determined according to the following

 

 

table.

 

PRI[1:2]

Upper Bank

Lower Bank

 

Priority

Priority

 

 

 

 

 

 

 

00

DMA Accesses

DMA Accesses

 

 

 

 

 

01

DMA Accesses

CPU Accesses

 

 

 

 

 

10

CPU Accesses

DMA Accesses

 

 

 

 

 

11

CPU Accesses

CPU Accesses

 

 

 

 

NOTE: The Motorola-recommended setting for the priority bits is 00.

5-2

MCF5282 User’s Manual

MOTOROLA

Page 138
Image 138
Motorola MCF5282 Sram Base Address Register Rambar, PRI1 PRI2 SPV, PRI1, PRI2, PRI12 Upper Bank Lower Bank Priority