Motorola MCF5282, MCF5281 Core Reset Status Register Crsr, Core Watchdog Control Register Cwcr

Register Descriptions

For details on the processor's view of the local SRAM memories, see Section 5.3.1, “SRAM Base Address Register (RAMBAR).”

8.4.3Core Reset Status Register (CRSR)

The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last type of reset that occurred. The CRSR is updated by the control logic when the reset is complete. Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect.

NOTE

The reset status register (RSR) in the reset controller module (see Chapter 28, “Reset Controller Module”) provides indication of all reset sources except the core watchdog timer.

7		6	5	4	0
Field	EXT	—	CWDR		—
Reset				See Note
R/W				R/W
Address				IPSBAR + 0x010

		Note: The reset value of EXT and CWDR depend on the last reset
		source. All other bits are initialized to zero.
		Figure 8-3. Core Reset Status Register (CRSR)
		Table 8-4. CRSR Field Descriptions
Bits	Name			Description
7	EXT	External reset.
		1 An external device driving	RSTI	caused the last reset. Assertion of reset by an external device
		causes the processor core to initiate reset exception processing. All registers are forced to their
		initial state.
6	—	Reserved, should be cleared.
5	CWDR	Core watchdog timer reset.
		1 The last reset was caused by the core watchdog timer. If CWRI in the CWCR is set and the core
		watchdog timer times out, a hard reset occurs.
4–0	—	Reserved, should be cleared.

8.4.4Core Watchdog Control Register (CWCR)

The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE]. By default it is disabled. If enabled, the watchdog timer requires the

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