Programming Model

24.5.3 I2C Control Register (I2CR)

The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation as a slave or a master.

7

6

5

4

3

2

1

0

Field

IEN

IIEN

MSTA

MTX

TXAK

RSTA

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

0000_0000

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

IPSBAR + 0x308

 

 

 

 

 

 

 

 

 

 

 

 

Figure 24-7. I2C Control Register (I2CR)

Table 24-4describes I2CR fields.

 

 

 

Table 24-4. I2CR Field Descriptions

 

 

 

 

Bits

Name

 

Description

 

 

 

7

IEN

I2C enable. Controls the software reset of the entire I2C module. If the module is enabled in the middle of a byte

 

 

transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is

 

 

detected. Master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus

 

 

cycle, ultimately causing either the current master or the I2C module to lose arbitration, after which bus

 

 

operation returns to normal.

 

 

0

The I2C module is disabled, but registers can still be accessed.

 

 

1

The I2C module is enabled. This bit must be set before any other I2CR bits have any effect.

6

IIEN

I2C interrupt enable.

 

 

0

I2C module interrupts are disabled, but currently pending interrupt condition are not cleared.

 

 

1

I2C module interrupts are enabled. An I2C interrupt occurs if I2SR[IIF] is also set.

5

MSTA

Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.

 

 

0

Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.

 

 

1

Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.

 

 

 

4

MTX

Transmit/receive mode select bit. Selects the direction of master and slave transfers.

 

 

0

Receive

 

 

1

Transmit. When the MCF5282MCF523x is addressed as a slave, software should set MTX according to

 

 

 

I2SR[SRW]. In master mode, MTX should be set according to the type of transfer required. Therefore, when

 

 

 

the MCF5282MCF523x addresses a slave device, MTX is always 1.

 

 

 

3

TXAK

Transmit acknowledge enable. Specifies the value driven onto SDA during acknowledge cycles for both master

 

 

and slave receivers. Note that writing TXAK applies only when the I2C bus is a receiver.

 

 

0

An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.

 

 

1

No acknowledge signal response is sent (that is, acknowledge bit = 1).

 

 

 

2

RSTA

Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.

 

 

0

No repeat start

 

 

1

Generates a repeated START condition.

 

 

 

1–0

Reserved, should be cleared.

 

 

 

 

24-8

MCF5282 User’s Manual

MOTOROLA

Page 518
Image 518
Motorola MCF5282, MCF5281 24.5.3 I2C Control Register I2CR, 4describes I2CR fields, I2CR Field Descriptions, IEN Iien, Ien