Motorola MCF5281 user manual MCF5282 Alphabetical Signal Index, Abbreviation Function

Overview

Table 14-2. MCF5282 Alphabetical Signal Index

	Abbreviation	Function			I/O
A[23:0]		Define the address of external byte, word, longword, and			I/O
		16-byte burst accesses.
AN[0:3]/AN[W:Z]		Direct analog input ANn, or multiplexed input ANx.			I
AN[52:53]/MA[0:1]		Direct analog input ANn, or multiplexed output MAn. MAn			I/O
		selects the output of the external multiplexer.
AN[55:56]/		Direct analog input ANn, or input TRIGn. TRIGn causes one of			I
TRIG[1:2]		the two queues to execute.
Breakpoint/		Signals a hardware breakpoint in debug mode		.	I
			(BKPT)
Test mode select		Provides information that determines JTAG test operation
		mode (TMS).
		Define the byte lane of data on the data bus.			I/O
BS[3:0]
CANRX		Controller area network transmit data.			I
CANTX		Controller area network transmit data.			O
CLKMOD[1:0]		Clock mode select			I
CLKOUT		Reflects the system clock.			O
		Programmed for a base address location and for masking			O
CS[6:0]
		addresses, port size and burst capability indication, wait state
		generation, and internal/external termination.
D[31:0]		Data bus. Provide the general purpose data path between the			I/O
		MCU and all other devices.
DDATA[3:0]		Display captured processor addresses, data, and breakpoint			O
		status.
DSO/TDO		Provides single-bit communication for debug module			O
		responses (DSO). Provides serial data port for outputting JTAG
		logic data (TDO).
DSI/TDI		Development serial clock for the serial interface to debug			I
		module (DSCLK). Asynchronously resets the internal JTAG
		controller to the test logic reset state (TRST).
		Provides single-bit communication for debug module			I
DSCLK/TRST
		commands (DSI). Provides serial data port for loading JTAG
		boundary scan, bypass, and instruction registers (TDI).
		Asserted to signify that a DRAM write cycle is underway.			O
DRAMW
		Negated to indicate a read cycle.
DTIN[3:0]		Clock the event counter or provide a trigger to timer value			I/O
		capture logic.
DTOUT[3:0]		Pulse or toggle on timer events.			I/O
ECOL		Asserted to indicate a collision.			I
ECRS		Asserted to indicate that the transmit or receive medium is not			I
		idle.
EMDC		Provides a timing reference to the PHY for data transfers on			O
		the EMDIO signal.

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