Motorola MCF5281, MCF5282 user manual Chapter Watchdog Timer Module

CONTENTS

Paragraph	Title	Page
Number		Number
17.5.1	Top Level Module Memory Map	17-20
17.5.2	Detailed Memory Map (Control/Status Registers)	17-20
17.5.3	MIB Block Counters Memory Map	17-21
17.5.4	Registers	17-23
17.6	Buffer Descriptors	17-45
17.6.1	Driver/DMA Operation with Buffer Descriptors	17-45
17.6.2	Ethernet Receive Buffer Descriptor (RxBD)	17-47
17.6.3	Ethernet Transmit Buffer Descriptor (TxBD)	17-49

Chapter 18

Watchdog Timer Module

18.1	Introduction	18-1
18.2	Low-Power Mode Operation	18-1
18.3	Block Diagram	18-2
18.4	Signals	18-2
18.5	Memory Map and Registers	18-2
18.5.1	Memory Map	18-2
18.5.2	Registers	18-3

Chapter 19

Programmable Interrupt Timer Modules (PIT0–PIT3)

19.1	Overview	19-1
19.2	Block Diagram	19-1
19.3	Low-Power Mode Operation	19-2
19.4	Signals	19-2
19.5	Memory Map and Registers	19-3
19.5.1	Memory Map	19-3
19.5.2	Registers	19-3
19.6	Functional Description	19-6
19.6.1	Set-and-Forget Timer Operation	19-6
19.6.2	Free-Running Timer Operation	19-7
19.6.3	Timeout Specifications	19-7
19.7	Interrupt Operation	19-8

Chapter 20

General Purpose Timer Modules

(GPTA and GPTB)

20.1	Features	20-1
20.2	Block Diagram	20-2

MOTOROLA Contents xiii