Memory Map

Table 6-4. CFMCR Field Descriptions

Bits

Name

 

Description

 

 

 

15–11

Reserved, should be cleared.

 

 

 

10

LOCK

Write lock control. The LOCK bit is always readable and is set once.

 

 

1

CFMPROT, CMFSACC, and CFMDACC register are write-locked.

 

 

0

CFMPROT, CMFSACC, and CFMDACC register are writable.

 

 

 

9

PVIE

Protection violation interrupt enable. The PVIE bit is readable and writable. The PVIE bit

 

 

enables an interrupt in case the protection violation flag, PVIOL, is set.

 

 

1

An interrupt will be requested whenever the PVIOL flag is set.

 

 

0

PVIOL interrupts disabled.

 

 

 

8

AEIE

Access error interrupt enable. The AEIE bit is readable and writable. The AEIE bit enables

 

 

an interrupt in case the access error flag, ACCERR, is set.

 

 

1

An interrupt will be requested whenever the ACCERR flag is set.

 

 

0

ACCERR interrupts disabled.

 

 

 

7

CBEIE

Command buffer empty interrupt enable. The CBEIE bit is readable and writable. CBEIE

 

 

enables an interrupt request when the command buffer for the Flash physical blocks is

 

 

empty.

 

 

1

Request an interrupt whenever the CBEIF flag is set.

 

 

0

Command buffer empty interrupts disabled

 

 

 

6

CCIE

Command complete interrupt enable. The CCIE bit is readable and writable. CCIE enables

 

 

an interrupt when the command executing for the Flash is complete.

 

 

1

Request an interrupt whenever the CCIF flag is set.

 

 

0

Command complete interrupts disabled

 

 

 

5

KEYACC

Enable security key writing. The KEYACC bit is readable and only writable if the KEYEN

 

 

bit in the CFMSEC register is set.

 

 

1

Writes to the Flash array are interpreted as keys to open the back door.

 

 

0

Writes to the Flash array are interpreted as the start of a program, erase, or verify

 

 

 

sequence.

 

 

 

4–0

Reserved, should be cleared.

 

 

 

 

6.3.4.2CFM Clock Divider Register (CFMCLKD)

The CFMCLKD is used to set the frequency of the clock used for timed events in program and erase algorithms.

Field

Reset

R/W

Address

7

6

5

0

DIVLD

PRDIV8

 

DIV

 

 

 

 

 

 

 

0000_0000

 

 

 

 

R

 

 

R/W

 

 

 

 

IPSBAR + 0x1D_0002

Figure 6-5. CFM Clock Divider Register (CFMCLKD)

All bits in CFMCLKD are readable. Bit 7 is a read-only status bit, while bits 6–0 can only be written once.

MOTOROLA

Chapter 6. ColdFire Flash Module (CFM)

6-9

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Motorola MCF5281 CFM Clock Divider Register Cfmclkd, Cfmcr Field Descriptions, Bits Name Description, Divld PRDIV8