Motorola MCF5281, MCF5282 user manual QASR0 Field Descriptions, CCW Pause Bit Response, Cwp

		Register Descriptions
		Table 27-10. QASR0 Field Descriptions
Bit(s)	Name	Description
15, 13	CFn	Queue completion flag. Indicates that a queue scan has been completed. CF[1:2] is set by the
		QADC when the input channel sample requested by the last CCW in the queue is converted,
		and the result is stored in the result table.
		When CFn is set and queue completion interrupts are enabled (QACRn[CIEn] = 1), the QADC
		requests an interrupt. The interrupt request is cleared when a 0 is written to the CF1 bit after it
		has been read as a 1. Once set, CF1 can be cleared only by a reset or by writing a 0 to it.
		CF[1:2] is updated by the QADC regardless of whether the corresponding interrupt is enabled.
		This allows polled recognition of the queue scan completion.
14, 12	PFn	Queue pause flag. Indicates that a queue scan has reached a pause. PF[1:2] is set by the QADC
		when the current queue 1 CCW has the pause bit set, the selected input channel has been
		converted, and the result has been stored in the result table.
		When PFn is set and interrupts are enabled (QACRn[PIEn] = 1), the QADC requests an
		interrupt. The interrupt request is cleared when a 0 is written to PFn, after it has been read as a
		1. Once set, PFn can be cleared only by reset or by writing a 0 to it.
		PF1:
		1 Queue 1 has reached a pause or gate closed before end-of-queue in gated mode.
		0 Queue 1 has not reached a pause or gate has not closed before end-of-queue in gated mode.
		PF2:
		1 Queue 2 has reached a pause.
		0 Queue 2 has not reached a pause.
		See Table 27-11for a summary of CCW pause bit response in all scan modes.
11–10	TORn	Queue trigger overrun flag. Indicates that an unexpected trigger event has occurred for queue
		1. TOR[1:2] can be set only while the queue is in the active state.
		Once set, TOR[1:2] is cleared only by a reset or by writing a 0 to it.
		1 At least one unexpected queue 1 trigger event has occurred or queue 1 reaches an
		end-of-queue condition for the second time in externally gated continuous scan.
		0 No unexpected queue 1 trigger events have occurred.
9–6	QS	Queue status. Indicates the current condition of queue 1 and queue 2. The two most significant
		bits are associated primarily with queue 1, and the remaining two bits are associated with queue
		2. Because the priority scheme between the two queues causes the status to be interlinked, the
		status bits must be considered as one 4-bit field. Table 27-12shows the bits in the QS field and
		how they denote the status of queue 1 and queue 2.
		The queue status field is affected by QADC stop mode. Because all of the analog logic and
		control registers are reset, the queue status field is reset to queue 1 idle, queue 2 idle.
		During debug mode, the queue status field is not modified. The queue status field retains the
		status it held prior to freezing. As a result, the queue status can show queue 1 active, queue 2
		idle, even though neither queue is being executed during freeze.
5–0	CWP	Command word pointer. Denotes which CCW is executing at present or was last completed.
		CWP is a read-only field with a valid range of 0 to 63; write operations have no effect.
		During stop mode, CWP is reset to 0 because the control registers and the analog logic are reset.
		When debug mode is entered, CWP is not changed; it points to the last executed CCW.

Table 27-11. CCW Pause Bit Response

Scan Mode	Queue Operation	PF Asserts?
Externally triggered single-scan	Pauses	Yes
Externally triggered continuous-scan	Pauses	Yes
Interval timer trigger single-scan	Pauses	Yes

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-23