Digital Control Subsystem

During queue execution, the QADC reads each CCW from the active queue and executes conversions in three stages:

Initial sample

Final sample

Resolution

During initial sample, a buffered version of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier.

During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. Each CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles. When an analog-to-digital conversion is complete, the result is written to the corresponding location in the result word table. The QADC continues to sequentially execute each CCW in the queue until the end of the queue is detected or a pause bit is found in a CCW.

When the pause bit is set in the current CCW, the QADC stops execution of the queue until a new trigger event occurs. The pause status flag bit is set, and an interrupt may optionally be requested. After the trigger event occurs, the paused state ends, and the QADC continues to execute each CCW in the queue until another pause is encountered or the end of the queue is detected.

An end-of-queue condition occurs when:

The CCW channel field is programmed with 63 to specify the end of the queue.

The end-of-queue 1 is implied by the beginning of queue 2, which is specified by the BQ2 field in QACR2.

The physical end of the queue RAM space defines the end of either queue.

When any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an interrupt is requested. These situations prematurely terminate queue execution:

Queue 1 is higher in priority than queue 2. When a trigger event occurs on queue 1 during queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the CCW in progress, and queue 1 execution begins. When queue 1 execution is complete, queue 2 conversions restart with the first CCW entry in queue 2 or the first CCW of the queue 2 subqueue being executed when queue 2 was suspended. Alternately, conversions can restart with the aborted queue 2 CCW entry. The RESUME bit in QACR2 selects where queue 2 begins after suspension. By choosing to re-execute all of the suspended queue 2 CCWs (RESUME = 0), all of the samples are guaranteed to have been taken during the same scan pass. However, a high trigger event rate for queue 1 can prevent completion of queue 2. If this occurs, execution of queue 2 can begin with the aborted CCW entry (RESUME = 1).

MOTOROLA

Chapter 27. Queued Analog-to-Digital Converter (QADC)

27-61

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Motorola MCF5281, MCF5282 user manual Queued Analog-to-Digital Converter Qadc 27-61