Motorola MCF5282, MCF5281 24.6 I2C Programming Examples, 24.5.5 I2C Data I/O Register I2DR

I2C Programming Examples

			Table 24-5. I2SR Field Descriptions (continued)
Bits	Name		Description
1	IIF	I2C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine.
		0	No I2C interrupt pending
		1	An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the
			following occurs:
		•	Complete one byte transfer (set at the falling edge of the ninth clock)
		•	Reception of a calling address that matches its own specific address in slave-receive mode
		•	Arbitration lost
0	RXAK	Received acknowledge. The value of SDA during the acknowledge bit of a bus cycle.
		0	An acknowledge signal was received after the completion of 8-bit data transmission on the bus
		1	No acknowledge signal was detected at the ninth clock.

24.5.5 I2C Data I/O Register (I2DR)

In master-receive mode, reading the I2DR, shown in Figure 24-9,allows a read to occur and initiates next byte data receiving. In slave mode, the same function is available once the I2C has received its slave address.

Field

Reset

R/W

Address

7 6 5 4 3 2 1 0

Data

0000_0000

R/W

IPSBAR + 0x310

Figure 24-9. I2C Data I/O Register (I2DR)

24.6 I2C Programming Examples

The following examples show programming for initialization, signaling START, post-transfer software response, signalling STOP, and generating a repeated START.

24.6.1 Initialization Sequence

Before the interface can transfer serial data, registers must be initialized, as follows:

1.Set I2FDR[IC] to obtain SCL frequency from the system bus clock. See Section 24.5.2, “I2C Frequency Divider Register (I2FDR).”

2.Update the I2ADR to define its slave address.

3.Set I2CR[IEN] to enable the I2C bus interface system.

4.Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not.

24-10 MCF5282 User’s Manual MOTOROLA