Motorola MCF5281, MCF5282 user manual Ethernet Transmit Buffer Descriptor TxBD

Buffer Descriptors

Table 17-36. Receive Buffer Descriptor Field Definitions (continued)

Word	Location	Field Name	Description
Offset + 0	Bit 1	OV	Overrun. Written by the FEC. A receive FIFO overrun occurred
			during frame reception. If this bit is set, the other status bits, M,
			LG, NO, CR, and CL lose their normal meaning and will be zero.
			This bit is valid only if the L-bit is set.
Offset + 0	Bit 0	TR	Will be set if the receive frame is truncated (frame length > 2047
			bytes). If the TR bit is set the frame should be discarded and the
			other error bits should be ignored as they may be incorrect.
Offset + 2	Bits [15:0]	Data Length	Data length. Written by the FEC. Data length is the number of
			octets written by the FEC into this BD’s data buffer if L = 0 (the
			value will be equal to EMRBR), or the length of the frame
			including CRC if L = 1. It is written by the FEC once as the BD
			is closed.
0ffset + 4	Bits [15:0]	A[31:16]	RX data buffer pointer, bits [31:16] 1
Offset + 6	Bits [15:0]	A[15:0]	RX data buffer pointer, bits [15:0]

1The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.

NOTE

Whenever the software driver sets an E bit in one or more receive descriptors, the driver should follow that with a write to RDAR.

17.6.3 Ethernet Transmit Buffer Descriptor (TxBD)

Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (R bit) when DMA of the buffer is complete. In the TxBD the user initializes the R, W, L, and TC bits and the length (in bytes) in the first longword, and the buffer pointer in the second longword.

The FEC will set the R bit = 0 in the first longword of the BD when the buffer has been DMA’d. Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 17.5.3, “MIB Block Counters Memory Map” for more details.

MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-49