Motorola MCF5281 Chapter Synchronous Dram Controller Module, Chapter DMA Controller Module

CONTENTS

Paragraph	Title	Page
Number		Number
14.2	MCF5282 External Signals	14-18
14.2.1	External Interface Module (EIM) Signals	14-18
14.2.2	SDRAM Controller Signals	14-21
14.2.3	Clock and Reset Signals	14-22
14.2.4	Chip Configuration Signals	14-22
14.2.5	External Interrupt Signals	14-23
14.2.6	Ethernet Module Signals	14-23
14.2.7	Queued Serial Peripheral Interface (QSPI) Signals	14-25
14.2.8	FlexCAN Signals	14-26
14.2.9	I2C Signals	14-26
14.2.10	UART Module Signals	14-26
14.2.11	General Purpose Timer Signals	14-27
14.2.12	DMA Timer Signals	14-28
14.2.13	Analog-to-Digital Converter Signals	14-29
14.2.14	Debug Support Signals	14-30
14.2.15	Test Signals	14-32
14.2.16	Power and Reference Signals	14-33

Chapter 15

Synchronous DRAM Controller Module

15.1	Overview	15-1
15.1.1	Definitions	15-1
15.1.2	Block Diagram and Major Components	15-2
15.2	SDRAM Controller Operation	15-3
15.2.1	DRAM Controller Signals	15-4
15.2.2	Memory Map for SDRAMC Registers	15-4
15.2.3	General Synchronous Operation Guidelines	15-9
15.2.4	Initialization Sequence	15-17
15.3	SDRAM Example	15-19
15.3.1	SDRAM Interface Configuration	15-20
15.3.2	DCR Initialization	15-20
15.3.3	DACR Initialization	15-21
15.3.4	DMR Initialization	15-22
15.3.5	Mode Register Initialization	15-23
15.3.6	Initialization Code	15-24

Chapter 16

DMA Controller Module

16.1	Overview	16-1
16.1.1	DMA Module Features	16-2

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