Motorola MCF5282, MCF5281 Edge Port, Watchdog Timer, Queued Analog-to-Digital Converter Qadc

Functional Description

The external CLKOUT output pin may be disabled in the low state to lower power consumption via the DISCLK bit in the SYNCR. The external CLKOUT pin function is enabled by default at reset.

7.3.2.18Edge Port

In wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes.

In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit the stop mode.

7.3.2.19Watchdog Timer

In stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes at the current value. When exiting these modes, the watchdog resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.

When not stopped, the watchdog may generate a reset to exit the low-power modes.

7.3.2.20Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)

In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.

When not stopped, the PIT may generate an interrupt to exit the low-power modes.

7.3.2.21Queued Analog-to-Digital Converter (QADC)

Setting the queued analog-to-digital converter (QADC) stop bit (QSTOP) will disable the QADC.

The QADC is unaffected by either wait or doze mode and may generate an interrupt to exit these modes.

Low-power stop mode (or setting the QSTOP bit), immediately freezes operation, register values, state machines, and external pins. This stops the clock signals to the digital electronics of the module and eliminates the quiescent current draw of the analog electronics. Any conversion sequences in progress are stopped. Exit from low-power stop mode (or clearing the QSTOP bit), returns the QADC to operation from the state prior to stop mode entry, but any conversions in progress are undefined and the QADC requires recovery time to stabilize the analog circuits before new conversions can be performed.

7-12 MCF5282 User’s Manual MOTOROLA