Motorola MCF5282, MCF5281 user manual Channel Decode and Multiplexer, Sample Buffer

Functional Description

Buffer		Final
		Sample	Resolution
Sample		Time:
Time:		n Cycles	Time:
2 Cycles	(2,4,8,16)		10 Cycles

QCLK

Sample Time

Successive Approximation Resolution Sequence

Figure 27-20. Conversion Timing

If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the CCW, the timing changes to that shown in Figure 27-21.See Section 27.6.7 for more information on the BYP field. The initial sample time is eliminated, reducing the potential conversion time by two QCLKs. When using the bypass mode, the external circuit should be of low source impedance (typically less than 10 kΩ). Also, the loading effects on the external circuitry of the QADC need to be considered, because the benefits of the sample amplifier are not present.

NOTE

Because of internal RC time constants, use of a two QCLK sample time in bypass mode will cause serious errors when operating the QADC at high frequencies.

		Sample			Resolution
			Time:
	n CYCLES					Time:
(2,4,8,16)					10 Cycles
QCLK
	Sample Time			Successive Approximation Resolution Sequence

Figure 27-21. Bypass Mode Conversion Timing

27.7.3.3Channel Decode and Multiplexer

The internal multiplexer selects one of the eight analog input signals for conversion. The selected input is connected to the sample buffer amplifier or to the sample capacitor. The multiplexer also includes positive and negative stress protection circuitry, which prevents deselected channels from affecting the selected channel when current is injected into the deselected channels.

27.7.3.4Sample Buffer

The sample buffer is used to raise the effective input impedance of the A/D converter, so that external factors (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is buffered onto the sample capacitor to reduce crosstalk between channels.

27-36 MCF5282 User’s Manual MOTOROLA